Search - actel uart

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[VHDL-FPGA-Verilog] UART_send DL : 0: Verilog HDL 串口发送程序，在ACTEL Fusion FPGA上实验成功，和大家一起分享！^_^-Verilog HDL send serial procedures, ACTEL Fusion FPGA in the success of the experiment, and share with everyone! ^ _ ^
Date : 2025-07-14 Size : 1kb User : whq
[VHDL-FPGA-Verilog] UART_rec DL : 0: verilog 串口接收程序，在ACTEL Fusion FPGA上实验成功和大家一起分享！^_^-Verilog serial receive process, ACTEL Fusion FPGA in the experimental success and share with everyone! ^ _ ^
Date : 2025-07-14 Size : 1kb User : whq
[Other Embeded program] UART DL : 0: 主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程，开发环境：LiberoIDE 8.5-The main chip: Actel' s FPGA030, Verilog language, the serial port to send and receive routines, development environment: LiberoIDE 8.5
Date : 2025-07-14 Size : 279kb User : grqd
[Com Port] Fusion_ABC_UART_2009_03_17 DL : 0: Actel Fusion System Management Development Kit UART Example. Contains Libero design using CoreABC. Program prints text to UART.
Date : 2025-07-14 Size : 6.67mb User : LoomVortex
[VHDL-FPGA-Verilog] Actel_Igloo_nano_UART DL : 0: This FPGA project include a simple version of the UART for Actel Igloo nano.
Date : 2025-07-14 Size : 443kb User : badfox
[SCM] uart DL : 0: 本程序的功能是实现串口通信，采用232传输协议，编码方式为8B/10B转换，即一位起始位，8位数据位，一位停止位，在actel Fusion系列开发板上得到验证，具有很强的通用性。本程序的编程语言为Verilog.-This procedure is to achieve the functions of serial communication, the transfer protocol is 232.The encoding protocol is 8B/10B , that is, a start bit, 8 data bits, one stop bit.It has been verified in the development-board of actel Fusion Series , and is highly versatile.The programming language used in this module is verilog.
Date : 2025-07-14 Size : 2kb User : 何斌
[VHDL-FPGA-Verilog] UART_LCD DL : 0: 基于Actel的Fusion系列FPGA的UART串口，带FIFO-Based on Actel s Fusion Series of FPGA serial UART with FIFO
Date : 2025-07-14 Size : 8kb User : 戚海峰
[VHDL-FPGA-Verilog] UART DL : 0: actel 公司 Fusion StartKit开发板串口实验，采用veilog 语言编写，易于理解-actel Company Fusion StartKit development board serial experiments using veilog language, easy to understand
Date : 2025-07-14 Size : 378kb User : anran
[VHDL-FPGA-Verilog] UART DL : 0: 基于Actel公司的硬件开发平台，实现异步通信-Based on Actel hardware development platform, and realize the asynchronous communication
Date : 2025-07-14 Size : 3.32mb User : 林鸿海
[VHDL-FPGA-Verilog] VerilogUart DL : 0: UART 串口通信模块，Verilog 实现。已在Microsemi Actel FPGA A3PE1500 硬件验证通过。-UART serial communication module, Verilog implementation. Verified by Microsemi Actel FPGA A3PE1500 hardware.
Date : 2025-07-14 Size : 946kb User :
[VHDL-FPGA-Verilog] CoreUartTest DL : 0: Actel FPGA UART 串口通信模块，调用Actel CoreUART IP核实现。已在Microsemi Actel FPGA A3PE1500 硬件验证通过。-Actel FPGA UART serial communication module, call Actel CoreUART IP core implementation. Verified by Microsemi Actel FPGA A3PE1500 hardware.
Date : 2025-07-14 Size : 817kb User :