actel Company Fusion StartKit development board serial experiments using veilog language, easy to understand

UART实验例程\Source\Fusion_UART\rec.v
............\......\...........\send.v
............\......\...........\uart_test.v
............\......\Fusion_UART
............\Source
............\Project\Fusion_UART\uart.prj
............\.......\...........\viewdraw\viewdraw.ini
............\.......\...........\........\wir
............\.......\...........\........\vf\project.lst
............\.......\...........\........\vf
............\.......\...........\........\sym
............\.......\...........\........\sch
............\.......\...........\viewdraw
............\.......\...........\synthesis\.recordref
............\.......\...........\.........\run_options.txt
............\.......\...........\.........\stdout.log
............\.......\...........\.........\traplog.tlg
............\.......\...........\.........\uart_test.areasrr
............\.......\...........\.........\uart_test.edn
............\.......\...........\.........\uart_test.fse
............\.......\...........\.........\uart_test.htm
............\.......\...........\.........\uart_test.map
............\.......\...........\.........\uart_test.sap
............\.......\...........\.........\uart_test.sdf
............\.......\...........\.........\uart_test.srd
............\.......\...........\.........\uart_test.srm
............\.......\...........\.........\uart_test.srr
............\.......\...........\.........\uart_test.srs
............\.......\...........\.........\uart_test.tlg
............\.......\...........\.........\uart_test_drc.rpt
............\.......\...........\.........\uart_test_sdc.sdc
............\.......\...........\.........\uart_test_syn.prj
............\.......\...........\.........\syntmp\sap.log
............\.......\...........\.........\......\uart_test.msg
............\.......\...........\.........\......\uart_test.plg
............\.......\...........\.........\......\uart_test_flink.htm
............\.......\...........\.........\......\uart_test_srr.htm
............\.......\...........\.........\......\uart_test_toc.htm
............\.......\...........\.........\syntmp
............\.......\...........\.........\....hesis_identify\uart_test.srs
............\.......\...........\.........\..................\uart_test.tlg
............\.......\...........\.........\..................\syntmp\identify.msg
............\.......\...........\.........\..................\......\uart_test.msg
............\.......\...........\.........\..................\......\uart_test_flink.htm
............\.......\...........\.........\..................\syntmp
............\.......\...........\.........\synthesis_identify
............\.......\...........\.........\backup
............\.......\...........\synthesis
............\.......\...........\.timulus\BtimErrors.log
............\.......\...........\........\files_to_build.txt
............\.......\...........\........\hdlsynchk.tcl
............\.......\...........\........\uart_test.dsk
............\.......\...........\........\uart_test.hpj
............\.......\...........\........\uart_test.v
............\.......\...........\........\uart_test_tbench.bk
............\.......\...........\........\uart_test_tbench.btim
............\.......\...........\........\uart_test_tbench.v
............\.......\...........\........\waveperl.log
............\.......\...........\stimulus
............\.......\...........\.martgen\smartgen.aws
............\.......\...........\smartgen
............\.......\...........\.imulation\meminit.dat
............\.......\...........\..........\modelsim.ini
............\.......\...........\..........\modelsim.ini.sav
............\.......\...........\simulation
............\.......\...........\phy_synthesis
............\.......\...........\hdl\hdlsynchk.tcl
............\.......\...........\...\rec.v
............\.......\...........\...\send.v
............\.......\...........\...\uart_test.v
............\.......\...........\hdl
............\.......\...........\designer\impl1\designer.log
............\.......\...........\........\.....\designer_genhdl.log
............\.......\...........\.......

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