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[Other resource] 组成原理课程设计--微程序控制器的设计完整报告 DL : 0: 首先利用实验系统COP2000具有完全开放的特性，由学生自行设计控制器微指令格式及定义，重新设计指令系统，要求该指令系统能够实现数据传送，进行加、减运算和无条件转移，具有累加器寻址、寄存器寻址、寄存器间接寻址、存储器直接寻址、立即数寻址等五种寻址方式。其次了解EDA扩展板功能，自学并掌握相关EDA技术，以实现EDA控制。-the first to use experimental system with a completely open COP2000 characteristics, designed by students controller microinstruction format and definition of re-engineering instruction, the instruction required to achieve data transmission, addition, subtraction and unconditional transfers, with accumulator addressing, registers addressable , register indirect addressing, directly addressable memory, the number of addressable immediately addressable five other way. Secondly understanding EDA expansion board functions, self-study and mastery of relevant EDA technology to achieve EDA control.
Date : 2008-10-13 Size : 320.27kb User : 晨风
[Other resource] dianzizhong DL : 0: 这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以直接下载,已经编译通过!-This is my learning process in the middle of the 10-minute program, containing various clock module and the counter, accumulator, and can download, compile!
Date : 2008-10-13 Size : 538.64kb User : 刘恒辉
[Other resource] FPGAprogram5 DL : 2: 数控振荡器的频率控制字寄存器、相位控制字寄存器、累加器和加法器可以用VHDL语言描述，集成在一个模块中，提供VHDL源程序供大家学习和讨论。 -NC oscillator frequency control word register, phase control word register, and processing instruments used accumulator can be used VHDL description, in an integrated modules provide VHDL source code for all learning and discussion.
Date : 2008-10-13 Size : 3.75kb User : 许嘉
[Other resource] 98632 DL : 0: GAL设计的累加器，译码器的原代码。已经测试成功，并且生成可烧写的JED文件！-GAL design accumulator, the decoder the original code. Has been tested successfully, and can generate the JED document burning!
Date : 2008-10-13 Size : 44.11kb User : 帅冲
[Other resource] MathNet.Numerics-v0.3 DL : 0: Math.NET开源数学库 C#实现具体功能: - A linear algebra package, see MathNet.Numerics.LinearAlgebra. - A sparse linear algebra package, see MathNet.Numerics.LinearAlgebra.Sparse. - Non-uniform random generators, see MathNet.Numerics.Generators. - Distribution fonctions, see MathNet.Numerics.Distributions. - Statistical accumulator, see MathNet.Numerics.Statistics. - Fourier transformations, see MathNet.Numerics.Transformations. - Miscellaneous utilies (polynomials, rationals, collections).-Math.NET revenue math C# achieve specific functions : - A linear algebra package, see MathNet.Numerics.LinearAlgebra. - A spar se linear algebra package, see MathNet.Numerics.LinearAlgebra.Sparse . - Non-uniform random generators. see MathNet.Numerics.Generators. - Distribu tion fonctions. see MathNet.Numerics.Distributions. - Stati stical accumulator, see MathNet.Numerics.Statistics. - Fourier t ransformations. see MathNet.Numerics.Transformations. - Mis cellaneous utilies (polynomials. rationals, collections).
Date : 2008-10-13 Size : 875.34kb User : 李华明
[Graph program] houghlines00 DL : 0: 直线Hough变换利用图像空间和Hough参数空间的点－线对偶性，把图像空间中的检测问题转换到参数空间。通过在参数空间里进行简单的累加统计，然后在Hough参数空间寻找累加器峰值的方法检测直线。-Hough transform space and the use of images Hough parameter space of point-line duality, transmit images of the space problem of detecting the change of the parameter space. Through the parameter space for a simple cumulative statistics, then Hough parameter space for accumulator peak detected straight.
Date : 2008-10-13 Size : 936byte User : david
[Graph program] houghpeaks00 DL : 0: 不用多说了，和Hogh搭配使用检测直线的程序直线Hough变换利用图像空间和Hough参数空间的点－线对偶性，把图像空间中的检测问题转换到参数空间。通过在参数空间里进行简单的累加统计，然后在Hough参数空间寻找累加器峰值的方法检测直线。-Needless to say, Hogh mix and the use of linear detection procedures Hough transform space and the use of images Hough parameter space The point-line duality, the image space detection switch to the parameter space. Through the parameter space for a simple cumulative statistics, then Hough parameter space for accumulator peak detected straight.
Date : 2008-10-13 Size : 1014byte User : david
[Software Engineering] PREDICTION.FRACTIONALN.SPURS DL : 0: Fast settling-time added to the already conflicting requirements of narrow channel spacing and low phase noise lead to Fractional4 divider techniques for PLL synthesizers. We analyze discrete \"beat-note spurious levels from arbitrary modulus divide sequences including those from classic accumulator methods.
Date : 2008-10-13 Size : 408.52kb User : 谢振
[assembly language] 键盘设计 DL : 0: 1，消除按键的抖动问题因为按键在闭合或断开过程中出现一段抖动期，主要由于按键的不稳定性引起的，这时会呈现一串页脉冲，时间的长短和开关的机械特性有关。一般在5ms~10ms之间。为保证CPU对键的一次闭合作一次处理，必须去抖动。在键的稳定闭合或断开时读键的状态。 2，据EICE51原理图编写并调试一个键输入子程序，其功能为判断键盘上有无键输入，若有键入，作去抖动处理后，计算输入键的键号送累加器A。-eliminate jitter button issues as keys or disconnect the closure process for some jitter period, mainly due to the instability of the keys to the cause, then it will result in a bunch of pages pulse, the duration and switches on the mechanical properties. General ~ 10ms between 5ms. To ensure that the CPU in a pair of keys a close cooperation, must go jitter. The key to the stability closed or disconnected when reading the key state. 2, EICE51 schematics prepared and debug a key input subroutine, and its function of determining whether keys on the keyboard input, if typing for to handle jitter, the admission of Bond, Bond sent accumulator A.
Date : 2008-10-13 Size : 832byte User : 叶文
[Other resource] 温度检测部分单片机程序 DL : 0: SRART: MOVX @R0,A 令ADC0809开始转换 WAIT: JB OP2.0,ADC 检测ADC0809转换完成否？ CALL DISP 调用显示子程序 JMP WAIT ADC:MOVX A,@R0 将转换好的数据送入累加器 CALL L1 调用十进制转换子程序 MOV RI,#OFFH 显示延时-SRART : R0 MOVX @ A change began to make ADC0809 WAIT : JB OP2.0, ADC conversion completed testing ADC0809 not? CALL DISP show subroutine call JMP WAIT ADC : MOVX A, @ R0 good data will be converted into the accumulator CALL L1 metric conversion subroutine call MOV RI, # OFFH show Delay
Date : 2008-10-13 Size : 3.88kb User : 刘浪
[Other] dds DL : 0: FPGA实现直接数字信号源.一个相位累加器的设计-FPGA realization of direct digital signal source. A phase accumulator design
Date : 2025-07-06 Size : 5kb User : 马彩青
[VHDL-FPGA-Verilog] accumulator DL : 0: 实现累加器的verilog源码，广泛应用在通信电路设计中-The realization of accumulator Verilog source, widely used in communication circuit design
Date : 2025-07-06 Size : 1kb User : 文明
[VHDL-FPGA-Verilog] dds_easy DL : 0: 直接频率合成DDS模块的ise工程，可以直接下载，在Spartan3/Spartan3E上验证通过。该DDS模块可以产生双通道的不同频率的正弦波，也可以产生同频的任意相位差的相移波形。本模块累加器位数为32位，可以产生12位相位精度12位量化精度的正弦波。该设计例化一个Block Ram，为节省储存空间仅需要储存1/4周期的数据。根据需要，可以重新修改数据，改变波形。-DDS direct frequency synthesizer module ，ise project, can be directly downloaded through the Spartan3/Spartan3E and tested successfully. The DDS module can generate two-channel sine wave of different frequency, or produce the same frequency arbitrary waveform phase difference of the phase shift. There is a 32-bit accumulator to generate 12 bit phase-precision 12-bit quantization precision of the sine wave. Cases the design of a Block Ram, in order to save storage space need to store only 1/4 cycle of data. Necessary, can modify data, change the waveform.
Date : 2025-07-06 Size : 460kb User : 郭先生
[Windows Develop] Desktop DL : 0: DDS数字频率合成DDS由相位累加器、正弦查找表、D／A转换器和低通滤波器组成 -DDS DDS DDS from the phase accumulator, sine look-up tables, D/A converter and low-pass filter composed of
Date : 2025-07-06 Size : 1kb User : chenxiaofeng
[VHDL-FPGA-Verilog] multiplier-accumulator(vhdl) DL : 0: 用VHDL语言描述和实现乘法累加器设计,4位的被乘数X和4位的乘数Y输入后，暂存在寄存器4位的寄存器A和B中，寄存器A和B的输出首先相乘，得到8位乘积，该乘积再与8位寄存器C的输出相加，相加结果保存在寄存器C中。寄存器C的输出也是系统输出Z。(原创，里面有乘法部分和累加部分可以单独提出来，很好用) -With the VHDL language to describe the design and realization of multiplier-accumulator, four of multiplicand X and 4-bit multiplier Y input, the temporary 4-bit registers in the register A and B, registers A and B multiplied by the output of the first, to be 8-bit product, the product further with the 8-bit output of register C, the sum of, the sum of the results stored in register C,. The output register C is also the system output Z. (Original, which are multiply and accumulate some part may be raised separately, very good use)
Date : 2025-07-06 Size : 945kb User : jlz
[VHDL-FPGA-Verilog] Accumulator DL : 0: 数字逻辑设计中累加器的开发源代码，开发环境为Quartus-Accumulator in Quartus
Date : 2025-07-06 Size : 311kb User : 陈轶博
[Game Server Simulator] flyffv15-Accumulator DL : 0: flyffv15 Accumulator 源码-flyffv15 Accumulator source
Date : 2025-07-06 Size : 12.57mb User : kljlj
[Other] accumulator DL : 0: accumulator max plus
Date : 2025-07-06 Size : 5kb User : rls1324
[VHDL-FPGA-Verilog] Verilog-Accumulator DL : 0: the folder contains two files written by Verilog HDL. the first one is an implementation of an accumulator that takes serial data as an input, and its output will be an accumulated sum of each consecutive four input samples. the second file is a test bench for the first file to test its operation
Date : 2025-07-06 Size : 1kb User : sawsan
[VHDL-FPGA-Verilog] Accumulator DL : 0: An 8-bit Accumulator with an adder module in Verilog HDL. You can change the bus width decoding the adder.
Date : 2025-07-06 Size : 6.66mb User : Patrick Go

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