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dds_easy

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 460kb
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  • Author :郭****
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Introduction - If you have any usage issues, please Google them yourself
DDS direct frequency synthesizer module ,ise project, can be directly downloaded through the Spartan3/Spartan3E and tested successfully. The DDS module can generate two-channel sine wave of different frequency, or produce the same frequency arbitrary waveform phase difference of the phase shift. There is a 32-bit accumulator to generate 12 bit phase-precision 12-bit quantization precision of the sine wave. Cases the design of a Block Ram, in order to save storage space need to store only 1/4 cycle of data. Necessary, can modify data, change the waveform.
Packet file list
(Preview for download)
project3
........\dcm1.vhd
........\dcm1.vhi
........\dcm1.xaw
........\dcm1_arwz.ucf
........\ddstop.vhd
........\pepExtractor.prj
........\project3.ipf
........\project3.ise
........\project3.mcs
........\project3.ntrc_log
........\project3.prm
........\project3.restore
........\project3.sig
........\project3_xdb
........\............\cst.xbcd
........\............\tmp
........\............\...\ise
........\............\...\...\version
........\............\...\...\__OBJSTORE__
........\............\...\...\............\Autonym
........\............\...\...\............\common
........\............\...\...\............\HierarchicalDesign
........\............\...\...\............\..................\HDProject
........\............\...\...\............\..................\.........\HDProject
........\............\...\...\............\..................\.........\HDProject_StrTbl
........\............\...\...\............\..................\__stored_object_table__
........\............\...\...\............\PnAutoRun
........\............\...\...\............\.........\Scripts
........\............\...\...\............\.........\.......\RunOnce_tcl
........\............\...\...\............\.........\.......\RunOnce_tcl_StrTbl
........\............\...\...\............\ProjectNavigator
........\............\...\...\............\................\dpm_project_main
........\............\...\...\............\................\................\dpm_project_main
........\............\...\...\............\................\................\dpm_project_main_StrTbl
........\............\...\...\............\................\................\NameMap
........\............\...\...\............\................\................\NameMap_StrTbl
........\............\...\...\............\................\__stored_objects__
........\............\...\...\............\................\__stored_objects___StrTbl
........\............\...\...\............\................\__stored_object_table__
........\............\...\...\............\ProjectNavigatorGui
........\............\...\...\............\...................\GuiProjectData
........\............\...\...\............\...................\GuiProjectData_StrTbl
........\............\...\...\............\SrcCtrl
........\............\...\...\............\.......\SavedOptions
........\............\...\...\............\STE
........\............\...\...\............\xreport
........\............\...\...\............\.......\Gc_RvReportViewer-Current-Module
........\............\...\...\............\.......\Gc_RvReportViewer-Current-Module_StrTbl
........\............\...\...\............\.......\Gc_RvReportViewer-Module-Data-testdds
........\............\...\...\............\.......\Gc_RvReportViewer-Module-Data-testdds_StrTbl
........\............\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default
........\............\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default_StrTbl
........\............\...\...\............\_ProjRepoInternal_
........\............\...\...\__REGISTRY__
........\............\...\...\............\Autonym
........\............\...\...\............\.......\regkeys
........\............\...\...\............\bitgen
........\............\...\...\............\......\regkeys
........\............\...\...\............\common
........\............\...\...\............\......\regkeys
........\............\...\...\............\cpldfit
........\............\...\...\............\.......\regkeys
........\............\...\...\............\Cs
........\............\...\...\............\..\regkeys
........\............\...\...\............\dumpngdio
........\............\...\...\............\.........\regkeys
........\............\...\...\............\fuse
........\............\...\...\............\....\regkeys
........\............\...\...\............\HierarchicalDesign
........\............\...\...\............\..................\HDProject
........\............\...\...\............\..................\.........\regkeys
........\............\.
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