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[Communication] verilog for uart

Description: 通用异步接收器/发送器(UART)是能够编程以控制计算机到附加串行设备的接口的微芯片。详细来说,它提供给计算机RS-...还有高级的UART提供了一定数量的数据缓冲,这样计算机和串行设备数据流就可以保持同样的速度。-universal asynchronous receiver / transmitter (UART) can be programmed to control computer attached to the serial device interface microchips. Details, provide it to the computer RS-High ... UART also provide a certain number of data buffer, computer equipment and serial data stream can maintain the same speed.
Platform: | Size: 9682 | Author: 李志 | Hits:

[Communication] verilog for uart

Description: 通用异步接收器/发送器(UART)是能够编程以控制计算机到附加串行设备的接口的微芯片。详细来说,它提供给计算机RS-...还有高级的UART提供了一定数量的数据缓冲,这样计算机和串行设备数据流就可以保持同样的速度。-universal asynchronous receiver/transmitter (UART) can be programmed to control computer attached to the serial device interface microchips. Details, provide it to the computer RS-High ... UART also provide a certain number of data buffer, computer equipment and serial data stream can maintain the same speed.
Platform: | Size: 9216 | Author: 李志 | Hits:

[VHDL-FPGA-Verilog] trellis_verlog

Description: ATSC发送端部分，ATSC标准特有的TCM编码，共6个文件，包含tb文件，已通过仿真，没有问题，verilog代码-ATSC transmitter, the ATSC standard TCM unique coding, a total of six documents, tb-contained documents, had passed through simulation, no problem, verilog code
Platform: | Size: 5120 | Author: 刘超 | Hits:

[ELanguage] async_transmitter

Description: 用verilog实现rs232通信async_transmitter.v-with verilog achieve rs232 communications async_transmitter.v
Platform: | Size: 1024 | Author: weixing | Hits:

[VHDL-FPGA-Verilog] 8251Verilog

Description: 通用串行异步收发器8251的Verilog HDL源代码,经过仿真验证。 -Universal Serial Asynchronous Receiver Transmitter 8251 the Verilog HDL source code, through simulation.
Platform: | Size: 15360 | Author: 钟兵 | Hits:

[VHDL-FPGA-Verilog] usart_verilog

Description: 通用串行异步收发器8251的Verilog HDL源代码.doc-Universal Serial Asynchronous Receiver Transmitter 8251 the Verilog HDL source code. Doc
Platform: | Size: 15360 | Author: 赵国柱 | Hits:

[VHDL-FPGA-Verilog] SPIsend

Description: Verilog HDL的程式，上網找到SPI程式， vspi.v這程式相當好用可用來接收與傳送SPI，並且寫了一個傳輸信號測試，spidatasent.v這程式就是傳送的資料，分別為00 66... 01 77...... 02 55這樣的資料，並透過MAX+PULS II軟體進行模擬，而最外層的程式是test_createspi.v！-Verilog HDL programs, Internet find SPI program, vspi.v this very useful program can be used to receive and send SPI, and wrote a transmission signal test, spidatasent.v this program is to send the information, namely, 00 66 ... 01 77 ...... 02 55 This information, and through the MAX+ PULS II software simulation, while the outermost layer of the program are test_createspi.v!
Platform: | Size: 145408 | Author: Rick | Hits:

[Industry research] UART_DESIGN

Description: The use of hardware description languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level description not only increases design productivity, but also provides unique advantages for design verification. The most dominant HDLs today are Verilog and VHDL. This application note illustrates the use of Verilog in the design and verification of a digital UART (Universal Asynchronous Receiver & Transmitter).
Platform: | Size: 141312 | Author: ltrko9kd | Hits:

[VHDL-FPGA-Verilog] A_bit_serial_data_transmitter

Description: 比特序列传送模块 把输入的八位比特数据 做循环后每个比特输出 详细请看英文描述-• To create Verilog-HDL modules written in the RTL style appropriate for both simulation and synthesis, for the various component parts of an Asynchronous Serial Data Transmitter. • To verify the correct behaviour of each component part by means of simulation. • To construct a top-level module corresponding to the Asynchronous Serial Data Transmitter, making use of the component parts developed above, and any additional behavioural elements which may be required. • To verify the correct operation of the top-level design by means of simulation using a Verilog-HDL test-fixture. • To automatically create a hierarchical logic diagram for the Asynchronous Serial Data Transmitter, generated using a Logic Synthesis tool.
Platform: | Size: 2048 | Author: 吴德昊 | Hits:

[VHDL-FPGA-Verilog] TRL_Design_of_a_asynchronous_bit_serial_data_trans

Description: RTL 异步数据传送模块 用verilog HDL 语言描述 输入为八比特数据，执行操作后异步每比特输出。-• To create Verilog-HDL module written in the RTL style appropriate for both simulation and synthesis, for an Asynchronous Serial Data Transmitter. • To verify the correct behaviour of the transmitter by means of simulation using a Verilog test-module. • To automatically create a logic diagram for the Asynchronous Serial Data Transmitter, generated using a Logic Synthesis tool.
Platform: | Size: 2048 | Author: 吴德昊 | Hits:

[VHDL-FPGA-Verilog] UARTtransmitter

Description: UART Transmitter. VHDL code and its testbench.
Platform: | Size: 2048 | Author: mehmet | Hits:

[VHDL-FPGA-Verilog] Transmitter

Description: UART Transmitter Verilog Code
Platform: | Size: 202752 | Author: gunkaragoz | Hits:

[VHDL-FPGA-Verilog] mydesign

Description: 基于FPGA的直接序列扩频发射机的设计与仿真。实验中以QuartusII 7.2 为设计和仿真工具， 各模块采用Verilog HDL设计并封装，顶层使用图形设计方式,最后得到的仿真结果使用Matlab描点来绘制出波形。 -FPGA-based direct sequence spread spectrum transmitter of the design and simulation. Experiment to QuartusII 7.2 for the design and simulation tools, the module using Verilog HDL to design and package, the top-level use of graphic design, and finally the simulation results obtained using the Matlab description points to draw waveforms.
Platform: | Size: 360448 | Author: fengjianhui | Hits:

[VHDL-FPGA-Verilog] xapp622

Description: 644 MHz SDR LVDS 发射器/接收器(verilog and doc)-644-MHz SDR LVDS Transmitter/Receiver
Platform: | Size: 355328 | Author: wicky | Hits:

[VHDL-FPGA-Verilog] UART

Description: the uart transmitter and receiver are used to design the data transmission for 8bit sipo and piso in verilog
Platform: | Size: 1024 | Author: prabakaran | Hits:

[Other] uart_rx

Description: Tcode is in VERILOG HDL (Hardware description language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL (Hardware description language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA
Platform: | Size: 1024 | Author: hassan | Hits:

[Communication-Mobile] Transmitter

Description: OFDM通信系统发送端完整verilog代码-OFDM communication system transmitter complete verilog code
Platform: | Size: 2273280 | Author: 王练 | Hits:

[OS Develop] SC16C752B

Description: The SC16C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s (3.3 V and 5 V). The SC16C752B offers enhanced features. It has a Transmission Control Register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during hardware and software flow control. With the FIFO Rdy register, the software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows on-board diagnostics.
Platform: | Size: 160768 | Author: 刘伟 | Hits:

[VHDL-FPGA-Verilog] DSSS

Description: 基于FPGA的我直接扩频序列发射机的quarters代码，-direct sequence transmitter
Platform: | Size: 2096128 | Author: olopgh | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 这是一本介绍verilog语言的书籍，verilog语言应用于FPGA，可实现诸多实时处理模块，例如实时OFDM发射机和接收机的制作-verilog for FPGA，real time OFDM Transmitter and receiver
Platform: | Size: 265216 | Author: k | Hits:
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