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[VHDL-FPGA-Verilog] gongcehngsheji_477-2

Description: 使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真-use of the VHDL simulation software in achieving RSC (recursive convolution system) code encoding and decoding hardware simulation
Platform: | Size: 6144 | Author: 李超 | Hits:

[Other] 3GPPjiaozhi

Description: 3Gpp 25.212 交织器 交织深度1024进行行内行间交织-3Gpp 25.212 intertwined depth interleaver 1,024 firms conducted between experts intertwined
Platform: | Size: 2048 | Author: 李春晖 | Hits:

[Communication] control

Description: Turbo码编码器时序控制模块，能够对于RAM，ROM读写以及编码器其他功能模块的使能进行控制-Turbo code encoder timing control module, to the RAM, ROM reader and encoder modules, other functions can be controlled so that
Platform: | Size: 1024 | Author: sunhao | Hits:

[DSP program] delete

Description: Turbo码编码器的删除模块，此模块是CCSDS标准系的码率为1/2和1/3的删除模块-Turbo code encoder to delete module, this module is the Department of CCSDS standard rate of 1/2 and 1/3 of the delete module
Platform: | Size: 1024 | Author: sunhao | Hits:

[Communication-Mobile] encode_finish

Description: Turbo码编码器的encode最上层模块，它的主要作用是连接Turbo码编码器的其他模块-Turbo code encoder encode top-level module, its main role is to connect the Turbo Code encoder other modules
Platform: | Size: 1024 | Author: sunhao | Hits:

[Other] rom

Description: Turbo码编码器的Rom宏模块，此模块中包含Rom.v文件和存储交织地址的.mif文件-Turbo code encoder Rom macro module, this module contains intertwined Rom.v documents and store addresses. Mif file
Platform: | Size: 9216 | Author: sunhao | Hits:

[VHDL-FPGA-Verilog] RSC

Description: Turbo码编码器的两个分量编码器RSC，主要由四个移位寄存器和两个模2加法器组成-Turbo code encoder of the two component encoders RSC, mainly by the four shift register and the two-mode adder composed of 2
Platform: | Size: 1024 | Author: sunhao | Hits:

[VHDL-FPGA-Verilog] EnergyEfficientVLSIArchitectureforLinearTurboEqua

Description: Energy efficient for turbo encoder decoder
Platform: | Size: 536576 | Author: suresh | Hits:

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