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[Other resource] divded-VHDL

Description: 一个简单的ＶＨＤＬ分频模块，可以嵌套自己的子程序实现任意分频-a simple VHDL-frequency module, which can be nested subroutine achieve their arbitrary frequency -
Platform: | Size: 2916 | Author: 林海 | Hits:

[Other resource] fenpin(vhdl)

Description: 使用VHDL编写的分频程序,能进行任意次的偶数分频,程序简单易懂,供 初学者参考-prepared by the use of VHDL-frequency procedures can make even the random frequency, the procedures are simple and easy to understand. reference for beginners
Platform: | Size: 154087 | Author: 黄鹏飞 | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl

Description: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Platform: | Size: 776192 | Author: 张涛 | Hits:

[VHDL-FPGA-Verilog] pinglvhecheng

Description: 程序用VHDL实现： 频率合成，DDS 主要调用LPM-procedures using VHDL : frequency synthesis, DDS major call LPM
Platform: | Size: 145408 | Author: 刘赛 | Hits:

[VHDL-FPGA-Verilog] frequency发生器

Description: vhdl语言实现的频率发生器，可以产生不同的频率-A frequency generator wirriten by VHDL, which can generate different frequecies.
Platform: | Size: 1024 | Author: xf | Hits:

[VHDL-FPGA-Verilog] 一个VHDL实现的测频计

Description: 一个vhdl实现的测频计,开发环境为任何支持vhdl语言的厂商提供的开发环境 -VHDL achieve a frequency measurement of dollars, development environment for any VHDL language support for manufacturers of the development environment
Platform: | Size: 1024 | Author: yaya | Hits:

[VHDL-FPGA-Verilog] 分频器VHDL描述

Description: 在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号时非常重要的。-in digital circuits, the need for regular high frequency clock operating frequency for hours, a lower frequency of the clock signal. We know that the hardware circuit design clock signal is very important.
Platform: | Size: 5120 | Author: 王力 | Hits:

[VHDL-FPGA-Verilog] 8倍频vhdl

Description: 该文件可用vhdl语言实现时钟8倍频，运行环境可在maxplus2和ise的仿真软件上-the document available VHDL Language 8 clock frequency, the operating environment and ideally maxplus2 simulation software
Platform: | Size: 1024 | Author: 罗兵武 | Hits:

[VHDL-FPGA-Verilog] GWDVPB

Description: 基于VHDL语言的高精度频率计的设计,已通过实验测试-based on VHDL frequency precision of the design, experimental test
Platform: | Size: 2048 | Author: 钟声 | Hits:

[VHDL-FPGA-Verilog] Frequency_counter

Description: VHDL语言写的频率计的程序，内带完整的技术报告-VHDL write the frequency of procedures, brought integrity of the technical report
Platform: | Size: 317440 | Author: 刘西圣 | Hits:

[VHDL-FPGA-Verilog] three-vhdl

Description: VHDL下实现3分频率波形,完整源代码,学习参考-VHDL under three frequency waveform, complete source code, study reference
Platform: | Size: 96256 | Author: 陈度甫 | Hits:

[VHDL-FPGA-Verilog] VHDL-six

Description: 用VHDL语言实现六分频，并且已经通过编译和仿真。由此可举一反三，实现任意偶数次分频。-VHDL six minutes frequency, and has been through translation, and simulation. From this we can draw a number at random dual frequency.
Platform: | Size: 25600 | Author: philohb | Hits:

[Documents] VHDL

Description: VHD设计实例8位加法器的设计分频电路数字秒表的设计-VHD Design 8 adder design of sub-frequency circuit design of digital stopwatch
Platform: | Size: 569344 | Author: yyy | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 一个直接数字频率合成的查表程序,VHDL语言,使用7128调试通过-A direct digital frequency synthesis of look-up table procedures, VHDL language, using 7128 debugging through
Platform: | Size: 147456 | Author: Chen.Y.M | Hits:

[VHDL-FPGA-Verilog] frequency-phase_test_vhdl

Description: 相位差测试，频率测试、频率计数器、闸门控制器、显示译码控制的vhdl程序-Phase tests, the frequency of testing, frequency counters, gate controller, showing decoding control VHDL procedures
Platform: | Size: 5120 | Author: 王充 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 用VHDL实现数字频率计,1. 时基产生与测频时序控制电路模块2. 待测信号脉冲计数电路模块3.锁存与译码显示控制电路模块4.顶层电路模块. -Using VHDL digital frequency meter, 1. Time-base generation and frequency measurement timing control circuit module 2. Analyte signal pulse counting circuit module 3. Latch and decoding display control circuit module 4. Top-level circuit module.
Platform: | Size: 13312 | Author: 侯治强 | Hits:

[VHDL-FPGA-Verilog] test

Description: VHDL实现倍频--偶数倍 分频电路 --分频倍数=2（n+1）-VHDL realize many times frequency multiplier circuit dual frequency multiplier = 2 (n+ 1)
Platform: | Size: 145408 | Author: 杨守望 | Hits:

[VHDL-FPGA-Verilog] epiano.vhdl

Description: 电子琴VHDL程序包含有：顶层程序、音阶发生器程序、数控分频模块程序和自动演奏模块程序-VHDL procedures flower contains: top-level procedures, scale generator procedures, numerical control frequency module procedures and module procedures performed automatically
Platform: | Size: 50176 | Author: 李立 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: VHDL经典设计 十进制 VHDL 频率计-VHDL classic design metric VHDL frequency counter
Platform: | Size: 277504 | Author: 刘思行 | Hits:

[VHDL-FPGA-Verilog] vhdl分频器设计

Description: vhdl分频器设计，用quartus软件偏写，可进行时钟的分频。(Design of VHDL frequency divider)
Platform: | Size: 279552 | Author: YXT800 | Hits:
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