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Title: vhdl分频器设计 Download
 Description: Design of VHDL frequency divider
 Downloaders recently: [More information of uploader 易晓]
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File list (Check if you may need any files):
FilenameSizeDate
4.txt 4510 2017-11-26
db 0 2017-12-31
db\prev_cmp_test41.qmsg 5128 2017-11-26
db\test41.(0).cnf.cdb 4054 2017-11-26
db\test41.(0).cnf.hdb 1418 2017-11-26
db\test41.cbx.xml 88 2017-11-26
db\test41.cmp.rdb 5877 2017-11-26
db\test41.cmp_merge.kpt 209 2017-11-26
db\test41.db_info 139 2017-11-26
db\test41.eda.qmsg 2651 2017-11-26
db\test41.hier_info 1595 2017-11-26
db\test41.hif 377 2017-11-26
db\test41.logic_util_heuristic.dat 0 2017-11-26
db\test41.lpc.html 372 2017-11-26
db\test41.lpc.rdb 402 2017-11-26
db\test41.lpc.txt 1060 2017-11-26
db\test41.map.ammdb 128 2017-11-26
db\test41.map.bpm 615 2017-11-26
db\test41.map.cdb 6512 2017-11-26
db\test41.map.hdb 13000 2017-11-26
db\test41.map.kpt 1440 2017-11-26
db\test41.map.logdb 4 2017-11-26
db\test41.map.qmsg 5128 2017-11-26
db\test41.map.rdb 1381 2017-11-26
db\test41.map_bb.cdb 1884 2017-11-26
db\test41.map_bb.hdb 9856 2017-11-26
db\test41.map_bb.logdb 4 2017-11-26
db\test41.pplq.rdb 299 2017-11-26
db\test41.pre_map.hdb 11569 2017-11-26
db\test41.pti_db_list.ddb 237 2017-11-26
db\test41.root_partition.map.reg_db.cdb 218 2017-11-26
db\test41.rtlv.hdb 11520 2017-11-26
db\test41.rtlv_sg.cdb 4437 2017-11-26
db\test41.rtlv_sg_swap.cdb 203 2017-11-26
db\test41.sld_design_entry.sci 269 2017-11-26
db\test41.sld_design_entry_dsc.sci 269 2017-11-26
db\test41.smart_action.txt 5 2017-11-26
db\test41.tis_db_list.ddb 237 2017-11-26
db\test41.tmw_info 67 2017-11-26
incremental_db 0 2017-12-31
incremental_db\compiled_partitions 0 2017-12-31
incremental_db\compiled_partitions\test41.db_info 139 2017-11-26
incremental_db\compiled_partitions\test41.root_partition.map.cdb 6267 2017-11-26
incremental_db\compiled_partitions\test41.root_partition.map.dpi 658 2017-11-26
incremental_db\compiled_partitions\test41.root_partition.map.hbdb.cdb 1474 2017-11-26
incremental_db\compiled_partitions\test41.root_partition.map.hbdb.hb_info 46 2017-11-26
incremental_db\compiled_partitions\test41.root_partition.map.hbdb.hdb 12705 2017-11-26
incremental_db\compiled_partitions\test41.root_partition.map.hbdb.sig 32 2017-11-26
incremental_db\compiled_partitions\test41.root_partition.map.hdb 12765 2017-11-26
incremental_db\compiled_partitions\test41.root_partition.map.kpt 1457 2017-11-26
incremental_db\README 653 2017-11-26
output_files 0 2017-12-31
output_files\test41.done 26 2017-11-26
output_files\test41.eda.rpt 2684 2017-11-26
output_files\test41.flow.rpt 8328 2017-11-26
output_files\test41.map.rpt 22692 2017-11-26
output_files\test41.map.summary 517 2017-11-26
simulation 0 2017-11-26
simulation\modelsim 0 2017-12-31
simulation\modelsim\modelsim.ini 11131 2017-11-26
simulation\modelsim\msim_transcript 2677 2017-11-26
simulation\modelsim\rtl_work 0 2017-12-31
simulation\modelsim\rtl_work\_info 1597 2017-11-26
simulation\modelsim\rtl_work\_lib.qdb 49152 2017-11-26
simulation\modelsim\rtl_work\_lib1_0.qdb 32768 2017-11-26
simulation\modelsim\rtl_work\_lib1_0.qpg 8192 2017-11-26
simulation\modelsim\rtl_work\_lib1_0.qtl 13855 2017-11-26
simulation\modelsim\rtl_work\_vmake 29 2017-11-26
simulation\modelsim\test41.vht 3206 2017-11-26
simulation\modelsim\test41.vht.bak 3200 2017-11-26
simulation\modelsim\test41_run_msim_rtl_vhdl.do 447 2017-11-26
simulation\modelsim\test41_run_msim_rtl_vhdl.do.bak 447 2017-11-26
simulation\modelsim\test41_run_msim_rtl_vhdl.do.bak1 447 2017-11-26
simulation\modelsim\test41_run_msim_rtl_vhdl.do.bak2 447 2017-11-26
simulation\modelsim\test41_run_msim_rtl_vhdl.do.bak3 447 2017-11-26
simulation\modelsim\test41_run_msim_rtl_vhdl.do.bak4 447 2017-11-26
simulation\modelsim\vsim.wlf 376832 2017-11-26
test41.qpf 1348 2017-11-26
test41.qsf 3847 2017-11-26
test41.qws 1849 2017-11-26
test41.vhd 1298 2017-11-26
test41.vhd.bak 608 2017-11-26
test41_nativelink_simulation.rpt 1005 2017-11-26

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