Search - UP DOWN COUNTER

[Windows Develop] counter

Description: 详细描述n比特计数器及RTL验证，计数器的位宽用generic语句设置为参数。MY_CNTR是一个n比特二进制的计数器，可以向上向下计数，并可设置计数值，计数器用异步的方式进行低电平复-A detailed description of n-bit counter and RTL verification, the bit counter is set to use generic parameters statement. MY_CNTR is an n-bit binary counter, counting down to up, and set of values, counters with asynchronous low-level approach to rehabilitation
Platform: | Size: 10240 | Author: chixiaobin | Hits:

[GIS program] Register

Description: -- Universal Register -- This design is a universal register which can be used as a straightforward storage register, a bi-directional shift register, an up counter and a down counter. -- The register can be loaded from a set of parallel data inputs and the mode is controlled by a 3-bit input. -- The termcnt (terminal count) output goes high when the register contains zero. -- download from: www.fpga.com.cn & www.pld.com.cn--- Universal Register -- This design is a universal register which can be used as a straightforward storage register, a bi-directional shift register, an up counter and a down counter. -- The register can be loaded from a set of parallel data inputs and the mode is controlled by a 3-bit input. -- The termcnt (terminal count) output goes high when the register contains zero. -- download from: www.fpga.com.cn & www.pld.com.cn
Platform: | Size: 4096 | Author: djs | Hits:

[VHDL-FPGA-Verilog] UpDownCounter

Description: an up down counter in verilog
Platform: | Size: 415744 | Author: ash | Hits:

[SCM] UpDownConter

Description: an up down counter for AVR
Platform: | Size: 2048 | Author: Ehsan | Hits:

[Other Embeded program] UP.DOWN.HEX.COUNTER

Description: Up down counter for microchip ASM code tested
Platform: | Size: 33792 | Author: mustafa | Hits:

[VHDL-FPGA-Verilog] UpDownCounter

Description: 8-Bit Up Down Counter Verilog Code
Platform: | Size: 306176 | Author: gunkaragoz | Hits:

[VHDL-FPGA-Verilog] up_down_counter

Description: 32 bit up/down counter with count enable based on altera fpga
Platform: | Size: 463872 | Author: abu_faisul | Hits:

[VHDL-FPGA-Verilog] bcd_updown_counter2

Description: It is a simple 4-digit bcd up down counter written in verilog
Platform: | Size: 1024 | Author: jason | Hits:

[Software Engineering] TB_Example_for_Students

Description: test bench for up down counter
Platform: | Size: 31744 | Author: Daniel R. | Hits:

[Other] counter

Description: a program for the up down counter with clk setting so that it can be ported directly on to fpga nexsys board
Platform: | Size: 484352 | Author: VINAY KUMAR GAUR | Hits:

[Software Engineering] counter

Description: Source code of a up/down counter in VHDL
Platform: | Size: 3072 | Author: flamestar | Hits:

[VHDL-FPGA-Verilog] 8bit_upDown_counter

Description: a simple 8 bit up/down counter, very handy and optimized
Platform: | Size: 2048 | Author: toon | Hits:

[VHDL-FPGA-Verilog] asagi_yukari_sayici_entity

Description: vhdl up down counter, entity,vhdl, good source code
Platform: | Size: 1024 | Author: asme | Hits:

[Graph program] 3digitUpDown16f84

Description: 3 digit up down pic counter
Platform: | Size: 274432 | Author: sasa | Hits:

[VHDL-FPGA-Verilog] up-down-counter

Description: up down counter by verilog
Platform: | Size: 673792 | Author: nedved | Hits:

[SCM] up-down-counter

Description: BASCOM-AVR:递增递减计数器项目：这是一个向上和向下计数器。这个项目包括两个红外传感器，该传感器连接到外部中断INT0和INT1。你可以使用任何感应器，甚至切换输入。-AVR Increment Decrement Counter Project: This is a up and down counter. this project consist of two infrared sensor that connected to Int0 and Int1 of External Interrupts. you can use any sensor or even switch for inputs.
Platform: | Size: 68608 | Author: lupo | Hits:

[Other] counter

Description: Up Down counter FPGA, VHDL
Platform: | Size: 550912 | Author: skawlsckd | Hits:

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[Windows Develop] counter

[GIS program] Register

[VHDL-FPGA-Verilog] UpDownCounter

[SCM] UpDownConter

[Other Embeded program] UP.DOWN.HEX.COUNTER

[VHDL-FPGA-Verilog] UpDownCounter

[VHDL-FPGA-Verilog] up_down_counter

[VHDL-FPGA-Verilog] bcd_updown_counter2

[Software Engineering] TB_Example_for_Students

[Other] counter

[Software Engineering] counter

[VHDL-FPGA-Verilog] 8bit_upDown_counter

[VHDL-FPGA-Verilog] asagi_yukari_sayici_entity

[Graph program] 3digitUpDown16f84

[VHDL-FPGA-Verilog] up-down-counter

[SCM] up-down-counter

[Other] counter

[Industry research] PIC16F877-Up-Down-Counter-Code

[VHDL-FPGA-Verilog] verilog-lfsr-updown-counter

[Other] Up-down converter

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