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[VHDL-FPGA-Veriloguartverlog

Description: 占用资源少的verilog HDL uart接口;采用固定波特率115200,可以修改程序中的分频来修改波特率,模式为1个启始位,8位数据位,1个停止位;带1字节缓存;当缓存空时输出空信号-Occupy fewer resources verilog HDL uart interface adopted a fixed baud rate of 115200, can modify the procedure to modify the baud rate frequency, the model of a start bit, 8 data bits, 1 stop bit with one word section of the cache when the cache empty space-time output signal
Platform: | Size: 2048 | Author: 张诚 | Hits:

[VHDL-FPGA-VerilogTLC549

Description: 实现对德州仪器厂生产的TLC549芯片的测试,产生符合规格的波形,并附上了仿真文件-Texas Instruments to achieve the TLC549 chip production tests have met the specifications of the waveform, together with the simulation file
Platform: | Size: 201728 | Author: king | Hits:

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