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[VHDL-FPGA-Verilog] stop_watch

Description: 采用Quartus2编写的电子秒表电路 实现计时、暂停等功能-Quartus2 prepared using electronic stopwatch timer circuit, suspension and other functions
Platform: | Size: 349184 | Author: gz208 | Hits:

[VHDL-FPGA-Verilog] Pld_lab4

Description: stop watch in vhdl using MAXII development board.
Platform: | Size: 1024 | Author: antish | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: 数字秒表的VHDL代码。当设计文件加载到目标器件后，设计的数字秒表从00-00-00开始计秒。，直到按下停止按键（按键开关S2）。数码管停止计秒。按下开始按键（按键开关S1），数码管继续进行计秒。按下复位按键（核心板上复位键）秒表从00-00-00重新开始计秒。-The VHDL code for digital stopwatch. When the design document loaded into the target device, the designed digital stopwatch count the seconds from the 00-00-00. Until you press stop key (key switch S2). Nixie tube stop count seconds. Press the start button (key switch S1), the digital control continue to count seconds. Press the reset button (core panel reset button) to restart the stopwatch count seconds from the 00-00-00.
Platform: | Size: 1024 | Author: 王唐小菲 | Hits:

[VHDL-FPGA-Verilog] Stopwatch

Description: Stop-watch for FPGA on 7 segment display
Platform: | Size: 6144 | Author: Aida | Hits:

[VHDL-FPGA-Verilog] EDA-experiments-based-on-VHDL

Description: 上传的文件包括E有关EDA实验的程序，比如FIFO，秒表，数字钟，七段数码管，状态机检测序列-The files uploaded contain some source code of EDA experiments based on VHDL, such as FIFO, digital clock, stop watch, digital tubes and sequential detector.
Platform: | Size: 4096 | Author: shi xin | Hits:

[VHDL-FPGA-Verilog] watchvhd

Description: WATCHVHD硬件描述语言(VHDL)是一个顶级的一个停表类型项目。-WATCHVHD is a top level VHDL type project of a Stop Watch.
Platform: | Size: 125952 | Author: linuxxx | Hits:

[VHDL-FPGA-Verilog] stopWatch

Description: 基于VHDL语言数字秒表的实现！使用模块化的设计，包含详细设计说明文档。可在DE2-115开发板上进行验证！-digital stop watch based on VHDL language
Platform: | Size: 493568 | Author: 顾庆水 | Hits:

[Other] stopwatch

Description: stop watch vhdl code
Platform: | Size: 159744 | Author: ali elgammal | Hits:

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