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[matlabKF_SINS_modify2

Description: 这是一个用MATLAB编写的接联惯性导航系统精对准阶段KALMAN滤波仿真程序的修正程序。解决了因系数矩阵条件数过大造成的滤波发散问题。-using MATLAB access Inertial Navigation System precision alignment stage Kalman filtering imitation really procedures amendment procedure. Solutions for the coefficient matrix several conditions caused by the excessive filtering divergence.
Platform: | Size: 2048 | Author: 吉庆昌 | Hits:

[Internet-Networklaserobstacleavoid

Description: 机器人障碍物避免和路径规划,适用于player/stage防真环境。-robot obstacle avoidance and path planning, applicable to the player/stage anti-real environment.
Platform: | Size: 4096 | Author: yuqingrui | Hits:

[VHDL-FPGA-Verilogadd_3p

Description: 3级流水线,含4元件的22位全加器的VHDL语言实现,适用于altera系列的FPGA-3-stage pipeline, with 4 components of 22 full adder realize the VHDL language, applicable to altera Series FPGA
Platform: | Size: 2048 | Author: wgx | Hits:

[matlabsimulink_process

Description: 这是一个矢量量化的simulink的仿真程序,通过smulink来实现多级矢量量化。-This is a vector quantization of the simulink simulation program, through smulink to realize multi-stage vector quantization.
Platform: | Size: 5120 | Author: 付彦 | Hits:

[VHDL-FPGA-VerilogDES_IP

Description: 有效的改进3-DES算法的执行速度,采用了多级流水线技术,设计了一种高速的硬件结构,使得原来需要48个时钟周期才能完成的运算,现在只需要一个时钟周期就可以完成。另外通过增加输入/输出的控制信号。使得该IP可以方便的集成到SOC中,大大缩短了SOC的设计周期。-Effective 3-DES algorithm to improve the implementation of speed, multi-stage pipeline technology, designed a high-speed hardware architecture, making the original 48 clock cycles required to complete the operation, and now only need one clock cycle can be completed. In addition by increasing the input/output control signal. Makes the IP can be easily integrated into the SOC, the SOC has significantly shortened the design cycle.
Platform: | Size: 23552 | Author: charity | Hits:

[VHDL-FPGA-Verilogfloat_data_multiple_use_fixed_pipeline_verilog_pro

Description: 采用fpga做小数运算的程序,使用了三级流水线技术,这是学习流水线和定点小数乘法很好的例子!-a program of float multiply, using 3-stage pipeline technology
Platform: | Size: 1024 | Author: xietianjiao | Hits:

[CommunicationMIMO(1)

Description: 在初始阶段,首先需要对所仿真的MIMO无线信道的仿真场景进行选择。仿真场景是指典型城区、恶劣城区、郊区或者乡村等信道传播环境,以及通信的方向,即是上行链路还是下行链路-At the initial stage, first of all, the need for the simulation of the MIMO wireless channel selection simulation scenario. Simulation refers to a typical urban scene, poor urban, suburban or rural environment, such as dissemination channels, as well as the direction of communication, that is, uplink or downlink
Platform: | Size: 141312 | Author: 立冬 | Hits:

[JSP/Javataxi-company-later-stage

Description: Project: taxi-company-later-stage This project provides a partial implementation of a simulation of taxis operating on a city grid to pick up and transport passengers. This is the fourth stage of this project. It illustrates the implementation of operation with multiple taxis. How to start this project: Create a Simulation object and invoke its run method. Use this version to explore further development ideas, such as implementation of the Shuttle class. -Project: taxi-company-later-stage This project provides a partial implementation of a simulation of taxis operating on a city grid to pick up and transport passengers. This is the fourth stage of this project. It illustrates the implementation of operation with multiple taxis . How to start this project: Create a Simulation object and invoke its run method. Use this version to explore further development ideas, such as implementation of the Shuttle class.
Platform: | Size: 46080 | Author: Li Yujie | Hits:

[ARM-PowerPC-ColdFire-MIPSpipeline

Description: 用Quartus II 设计的3级流水CPU,指令采用二次重叠执行方式-Quartus II design with three-stage pipeline CPU, instruction execution overlaps with the second time
Platform: | Size: 3028992 | Author: kevin | Hits:

[Software Engineeringjifenlvboqi

Description: 为了解决软件无线电通信系统中频采样之后的极大数据量在基带处理部分对DSP计算的压力,常采用多速率处理技术.多速率处理过程中需要使用积分梳状滤波器、半带滤波器和高阶FIR滤波器.在分析了积分梳状滤波器的结构和特性的基础上,阐述了多级CIC滤波器一种高效的FPGA实现方法,该方法的正确性和可行性通过Quartus Ⅱ的时序仿真分析得以验证,实际中可以推广应用.-In order to solve software-defined radio communications system after IF sampling of great amount of data to the DSP in the baseband processor part of the calculation of the pressure, often using multi-rate processing technology. Multi-rate processing need to use the integrator comb filter, half-band filters and high-order FIR filter. in the analysis of the integrator comb filter structure and characteristics, based on the multi-stage CIC filter described an efficient FPGA implementations, the correctness and feasibility of the method adopted by the timing Quartus Ⅱ simulation analysis can be verified in practice can be applied.
Platform: | Size: 180224 | Author: 王楚宏 | Hits:

[Graph programprogram

Description: 可以将分割完的子图像进行二值化,二值化效果很明显,易于下一步的分割识别-You can split end of the sub-image binarization, thresholding effect is obvious and easy to identify the next stage of segmentation
Platform: | Size: 2048 | Author: 梁勇 | Hits:

[matlabonekftwostagekf

Description: Two-stage kalman filter
Platform: | Size: 2048 | Author: Chiang | Hits:

[Software EngineeringA-multi-stage-vendor-selection-mixed-integer-progr

Description: 一种多阶段供应商选择的混合整数规划模型A multi-stage vendor selection mixed integer programming model-A multi-stage vendor selection mixed integer programming model
Platform: | Size: 133120 | Author: zhejiang001 | Hits:

[Software EngineeringWH_T27_2007-stage-achinery-Acceptance-Test-Procedu

Description: WH_T27_2007舞台机械验收检测程序WH_T27_2007 stage machinery Acceptance Test Procedures-WH_T27_2007 stage machinery Acceptance Test Procedures
Platform: | Size: 1454080 | Author: guangdong1234 | Hits:

[Windows Developmulti.stage.amplifier.circuit.document

Description: 多级放大电路开发设计经典文档Development of multi-stage amplifier circuit design classic document -Development of multi-stage amplifier circuit design classic document
Platform: | Size: 475136 | Author: wangnan | Hits:

[VHDL-FPGA-Verilogpipelined-mips-cpu

Description: 用verilog语言描述了MIPS的5级流水线。-Language described by verilog MIPS 5-stage pipeline.
Platform: | Size: 171008 | Author: jack chen | Hits:

[VHDL-FPGA-Verilogcpu

Description: 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
Platform: | Size: 2048 | Author: dylan | Hits:

[Communication-MobileTwo-Stage Channel Estimation for Low SHF Band

Description: 提出一种新的信道估计算法,在二级信道估计和低超频带。(A new channel estimation algorithm is proposed, in which two stage channel estimation and low over band are employed.)
Platform: | Size: 389120 | Author: `weishao | Hits:

[OtherStage-3.2.2-Source.tar

Description: robot 仿真模拟,开源系统,功能强大,linux系统支持(Player/Stage is an open software project built and maintained by the international academic robotics community, available through SourceForge. robot sys)
Platform: | Size: 1102848 | Author: ldhe | Hits:

[Program docstage pfa

Description: stage was designed to select different cluster heads in a field according to the amount of energy that is distributed in relation to a neighboring node
Platform: | Size: 70144 | Author: abdelteffah | Hits:
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