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[VHDL-FPGA-Verilog] spi

Description: VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the
Platform: | Size: 65536 | Author: 阿飞 | Hits:

[VHDL-FPGA-Verilog] spi_op_core

Description: 串行数据SPI master的开源控制器，verilog，内附说明-SPI master serial data open-source controller, verilog, containing a description
Platform: | Size: 81920 | Author: 王天 | Hits:

[VHDL-FPGA-Verilog] SPI_collect

Description: 有关SPI的vhdl实现。包括SPI官方协议，几篇开发时用到的论文，附加了中文注释的SPI IPcore，还有一个经过简化的master mode的SPI实现的vhdl代码-Related to the VHDL SPI realize. Including SPI official agreement, when used to develop several theses, Chinese notes attached SPI IPcore, there is a simplified master mode the SPI realize the VHDL code
Platform: | Size: 1334272 | Author: danielmu | Hits:

[VHDL-FPGA-Verilog] spi_master

Description: 基于CPLD/FPGA的SPI控制的IP核的实现spi_master-Based on CPLD/FPGA to control the SPI realize the IP core spi_master
Platform: | Size: 1024 | Author: linsky | Hits:

[Embeded-SCM Develop] spiinterfaceverilog

Description: SPI Master Core Specification，This document provides specifications for the SPI (Serial Peripheral Interface) Master core-SPI Master Core Specification, This document provides specifications for the SPI (Serial Peripheral Interface) Master core
Platform: | Size: 82944 | Author: 贾远鸿 | Hits:

[Com Port] spi

Description: SPI master的verilog代码-Verilog code for SPI master
Platform: | Size: 2048 | Author: xudong | Hits:

[Other] spi.tar

Description: This is a verilog code used oversampled clock to implement SPI slave. Also include C code for a ARM processor as the SPI master-This is a verilog code used oversampled clock to implement SPI slave
Platform: | Size: 1024 | Author: johnl | Hits:

[VHDL-FPGA-Verilog] spi_master_control

Description: VHDL SPI 控制器FPGA官网提供-VHDL SPI controller FPGA to provide official website
Platform: | Size: 670720 | Author: lonely_vv | Hits:

[Other] spi_master

Description: SPI wishbone master and verification environment
Platform: | Size: 2506752 | Author: 王小墨 | Hits:

[Embeded-SCM Develop] spi_core_open

Description: SPI 设计 为主机设计，供大家参考,希望对大家有用-SPI master design
Platform: | Size: 96256 | Author: 迪 | Hits:

[VHDL-FPGA-Verilog] FPGASPI

Description: 用FPGA实现主SPI程序,包含开发工程、测试文件和源文件代码-fpga design the SPI code
Platform: | Size: 301056 | Author: Lee | Hits:

[VHDL-FPGA-Verilog] spi_master

Description: SPI接口的实现以及对外设的读写操作，其中包扩了几种工作方式，同时可以读取外设的版本号，传输速率可以达到2Mbps-SPI interface implementation, as well as read and write operations on the peripheral, which extended several work packages at the same time can read the version number of peripherals, transfer rate up to 2Mbps
Platform: | Size: 1024 | Author: guoguo | Hits:

[MPI] spi_verilog

Description: 实现SPI MASTER功能，并有仿真代码和仿真结果。-To achieve SPI MASTER function, and a simulation code and simulation results.
Platform: | Size: 45056 | Author: davi_insist | Hits:

[Embeded-SCM Develop] SPI_TEST

Description: The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. Sometimes SPI is called a "four wire" serial bus, contrasting with three, two, and one wire serial buses.-The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. Sometimes SPI is called a "four wire" serial bus, contrasting with three, two, and one wire serial buses.
Platform: | Size: 478208 | Author: wei | Hits:

[Software Engineering] conjoined

Description: SPI protocol: Serial Periphral Interface with both slave and master incorporated-SPI protocol: Serial Periphral Interface with both slave and master incorporated
Platform: | Size: 1024 | Author: smik | Hits:

[VHDL-FPGA-Verilog] l1ghVhVI

Description: The VSPI core implements an SPI interface compatible with the many -- serial EEPROMs, and microcontrollers. The VSPI core is typically used -- as an SPI master, but it can be configured as an SPI slave as well.
Platform: | Size: 226304 | Author: aaa | Hits:

[VHDL-FPGA-Verilog] SpiMaster

Description: This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate
Platform: | Size: 9216 | Author: RutaliMulye | Hits:

[VHDL-FPGA-Verilog] SPI-Master-Core-DAC-ADC-spartan

Description: SPI Master Core for spartan (ADC, DAC) vhdl code
Platform: | Size: 1961984 | Author: onur | Hits:

[VHDL-FPGA-Verilog] SPI-master-P-tb

Description: SPI master VHDL realisation Also contains TestBench
Platform: | Size: 2048 | Author: Stan | Hits:

[Other] SPI

Description: 使用VHDL写的SPI Master模块(Using the SPI Master module written in VHDL)
Platform: | Size: 2048 | Author: BY冬子 | Hits:
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