Description: 本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考.-this code is used to write the language VRILOG SDRAM controller standard code for the development of SARM reference. Platform: |
Size: 776597 |
Author:汪旭 |
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Description: 本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考.-this code is used to write the language VRILOG SDRAM controller standard code for the development of SARM reference. Platform: |
Size: 776192 |
Author:汪旭 |
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Description: verilog 代码,读写SDRAM 不带仿真,需要自己编写测试文件-Verilog code, read and write SDRAM simulation without the need to prepare their own test documentation Platform: |
Size: 19935232 |
Author:ch |
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Description: 标准SRD SDRAM控制器参考设计,altera提供
Verilog代码,带有使用手册,大家试试交流一下
-Standard SRD SDRAM controller reference design, altera provide Verilog code, with user manual, we try to exchange some Platform: |
Size: 776192 |
Author:费尔德 |
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Description: 基于FPGA的SDRAM控制器Verilog代码,开发环境为Quartus6.1,控制SDRAM实现对同一片地址先写后读。-FPGA-based SDRAM controller Verilog code, development environment for Quartus6.1, control of SDRAM to achieve the same address one after the first time to write. Platform: |
Size: 26624 |
Author:姜琰俊 |
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Description: 数字信号处理的FPGA实现(Uwe Meyer-Baese)书中例子的Verilog代码-FPGA implementation of digital signal processing (Uwe Meyer-Baese) book example of Verilog code for Platform: |
Size: 330752 |
Author:lin |
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Description: 清华大学sdr项目,网口代码。Verilog编写。很实用。希望大家喜欢。-Tsinghua University sdr project, network interface code. Verilog preparation. Very practical. Hope you like it. Platform: |
Size: 4096 |
Author:柳承化 |
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Description: 使用verilog HDL写的sdram(SDR)的控制器源代码,具有很好的可移植性,试验的例子已经通过QuartusII 9.0编译通过,可以运行在cycloneII上-Controller source code using verilog HDL written in the sdram (SDR), has good portability, test examples via the QuartusII 9.0 compiler, you can run in cycloneII Platform: |
Size: 20480 |
Author:李立鸣 |
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