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[VHDL-FPGA-Verilog] POS_PHY_RTL

Description: VERILOG五POSPHY LEVEL3电路描述，可综合,已经过检验.-Five POSPHY LEVEL3 Verilog circuit description can be integrated, has been tested.
Platform: | Size: 62464 | Author: 徐新颜 | Hits:

[Other] fpga_mac_vhdl

Description: 针对嵌入式系统的底层网络接口给出了一种由FPGA实现的以太网控制器的设计方法．该控制器能支持10Mbps和100Mbps的传输速率以及半双工和全双工模式，同时可提供MII接口，可并通过外接以太网物理层（PHY）芯片来实现网络接入 -Embedded systems for the bottom of this paper, a network interface from FPGA to achieve the Ethernet controller design method. The controller will support the 10Mbps and 100Mbps transfer rate, as well as half-duplex and full-duplex mode, at the same time provides MII interface, and through external Ethernet physical layer (PHY) chip to achieve network access
Platform: | Size: 316416 | Author: 林大朋 | Hits:

[VHDL-FPGA-Verilog] sata_device_model

Description: sata_device_model,对做硬盘控制器的朋友有帮助-sata_device_model, to make the hard disk controller has a friend help
Platform: | Size: 17412096 | Author: 磊 | Hits:

[VHDL-FPGA-Verilog] MAC

Description: Verilog code for MAC
Platform: | Size: 1053696 | Author: dheeru | Hits:

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[VHDL-FPGA-Verilog] POS_PHY_RTL

[Other] fpga_mac_vhdl

[VHDL-FPGA-Verilog] sata_device_model

[VHDL-FPGA-Verilog] MAC

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