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[Other resource] wbm

Description: 用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core.-algorithm using the symbols multiplier, HDL-piece quantities. it is not necessary for the company's paid Multiplier ip core.
Platform: | Size: 2671 | Author: 蒋雯丽 | Hits:

[Other resource] 经典高速乘法器IP

Description: 乘法器是硬件设计中的很常见也很重要的一个模块，它的VHDL硬件实现很好的解决了软件编程中做乘法速度慢的问题，在实时高速系统应用中或DSP软核或数字信号处理硬件实现算法中，经常能使用到乘法器，所以经典的高速乘法器IP 很有参考价值-Multiplier is a common and important module in hardware designing.Its VHDL addresses the low speed of multiplication in software programming. Multiplier is often used in real-time high-speed system application , DSP soft core or hardware implementation of digital signal processing,so it is worthful to know classic high-speed multiplier IP
Platform: | Size: 309363 | Author: czy | Hits:

[VHDL-FPGA-Verilog] 经典高速乘法器IP

Description: 乘法器是硬件设计中的很常见也很重要的一个模块，它的VHDL硬件实现很好的解决了软件编程中做乘法速度慢的问题，在实时高速系统应用中或DSP软核或数字信号处理硬件实现算法中，经常能使用到乘法器，所以经典的高速乘法器IP 很有参考价值-Multiplier is a common and important module in hardware designing.Its VHDL addresses the low speed of multiplication in software programming. Multiplier is often used in real-time high-speed system application , DSP soft core or hardware implementation of digital signal processing,so it is worthful to know classic high-speed multiplier IP
Platform: | Size: 309248 | Author: czy | Hits:

[VHDL-FPGA-Verilog] wbm

Description: 用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core.-algorithm using the symbols multiplier, HDL-piece quantities. it is not necessary for the company's paid Multiplier ip core.
Platform: | Size: 2048 | Author: 蒋雯丽 | Hits:

[Other] DesignofVeryDeepPipelinedMultipliersforFPGAs(IEEE)

Description: 关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work investigates the use of very deep pipelines forimplementing circuits in FPGAs, where each pipelinestage is limited to a single FPGA logic element (LE). Thearchitecture and VHDL design of a parameterized integerarray multiplier is presented and also an IEEE 754compliant 32-bit floating-point multiplier. We show how towrite VHDL cells that implement such approach, and howthe array multiplier architecture was adapted. Synthesisand simulation were performed for Altera Apex20KEdevices, although the VHDL code should be portable toother devices. For this family, a 16 bit integer multiplierachieves a frequency of 266MHz, while the floating pointunit reaches 235MHz, performing 235 MFLOPS in anFPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and otherconsiderations to apply the technique in real designs arealso addressed.
Platform: | Size: 179200 | Author: 李中伟 | Hits:

[Other] altclklock

Description: 如何给时钟倍频或者分频，以及altera提供的IP核使用方法-How to clock multiplier or divider, as well as to provide the IP of nuclear altera use
Platform: | Size: 2048 | Author: 杨华 | Hits:

[Algorithm] xapp371

Description: xilinx里的乘法器ip核程序，booth乘法 wallace tree算法 4-2压缩编码 超前进位加法-Xilinx multiplier ip
Platform: | Size: 87040 | Author: 王凯 | Hits:

[VHDL-FPGA-Verilog] pll

Description: 利用qaurtus的内的ip核定制锁相环实现对信号的倍频-The use of the ip qaurtus approved system PLL multiplier on signal
Platform: | Size: 1370112 | Author: 唐军 | Hits:

[Com Port] shiyanbaogao

Description: 了解ISE平台的基本环境，编译程序，在MC8051 IP核中，要求实现：增加PLL锁相环，扩大内部RAM，定时器，串口和外部中断等资源，并增加乘法器和除法器的功能。-ISE platform to understand the basic environment, compiler, the MC8051 IP core, the requirement to achieve: increased PLL phase-locked loop, expanding the internal RAM, timers, serial port and external interrupts, and other resources, and increase the multiplier and divider functions.
Platform: | Size: 149504 | Author: liujia | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: this document describe a 8 * 8 bits mutiplier with vhdl using booth algorithm and shown all parts of implementing this ip by ise software
Platform: | Size: 2065408 | Author: seif | Hits:

[VHDL-FPGA-Verilog] fft

Description: 基于VHDL语言编写的FFT程序，256点，旋转因子存在自己编写的ROM里面，乘法器和数据存储采用的是IP核-FFT-based program written in VHDL, 256 points, there is rotation factor which I have written the ROM, multiplier, and data storage is used in IP core
Platform: | Size: 6144 | Author: 胡佳 | Hits:

[VHDL-FPGA-Verilog] multiplier_ip

Description: 基于IP核的乘法器设计，multiplier_ip中包含完整的工程设计文件，用户可以在Xilinx ISE下运行-Based on IP core of design, multiplier_ip on time-multiplier contain complete engineering documents, users can run Xilinx ISE
Platform: | Size: 2784256 | Author: chenlan | Hits:

[VHDL-FPGA-Verilog] di3

Description: IP核和乘法运算模块分别有两个输入端口a、b和clk时钟脉冲信号及一个输出端口p，用例化语句将这两个模块合成一个乘法器后就生成了由两个输入端口a、b和clk时钟脉冲信号及两个输出端口p1、p2组成。-IP cores and multiplication module respectively, the two input ports of a, b, and clk clock signal and an output port p, these two modules with the instantiation statements Synthesis of a multiplier by two input ports, a, b are generated after and the the CLK clock pulse signals and two output ports p1, p2.
Platform: | Size: 1024 | Author: 吴凤妹 | Hits:

[MiddleWare] MULTI4BIT

Description: 4位乘法器由于所使用的软件是ISE，没有LPM_ROM可以直接调用，所以此设计直接调用的乘法器的IP核来完成此功能，达到同样的效果。-Four multiplier
Platform: | Size: 66560 | Author: 李丽 | Hits:

[VHDL-FPGA-Verilog] multiplier_ip

Description: 基于IP核的乘法器设计，完整的设计工程文件在multiplier_ip文件夹下-IP-based core multiplier design, complete design engineering file multiplier_ip file folder
Platform: | Size: 3463168 | Author: xiebaiyuan | Hits:

[VHDL-FPGA-Verilog] clk_DCM_50to75MHz

Description: 调用ISE010.1的IP核DCM来实现频率倍增，本程序实现的是50MHz到75MHz的倍增，开发者可以根据DCM的参数设置实现不同频率的倍增-Call ISE010.1 IP core DCM to achieve frequency doubling, the program is 50MHz to 75MHz multiplication, developers can implement different parameter settings of DCM frequency multiplier
Platform: | Size: 1024 | Author: wulei | Hits:

[VHDL-FPGA-Verilog] sss

Description: 使用Verilog语言编写源代码.调用一些基本的IP核，如DCM模块、DDS模块ChipScope模块、乘法器模块等来实现调制.最后通过编程并利用FPGA板子实现AM、DBS、SSB的调制。-Using Verilog language source code. Invoke some basic IP cores, such as DCM module, DDS module ChipScope modules, multiplier module to achieve modulation. Finally realize AM, DBS, SSB modulation by programming and the use of FPGA board.
Platform: | Size: 1825792 | Author: Blus | Hits:

[VHDL-FPGA-Verilog] complexMul

Description: 复数乘法器，利用ISE里的float IP核，实现了32位复数的乘法-Complex multiplier, using the ISE in the float IP core to achieve the 32 complex multiplications
Platform: | Size: 1024 | Author: 徐天伟 | Hits:

[VHDL-FPGA-Verilog] dfe_filter

Description: DEF算法的FIR滤波器verilog代码，内有乘法器IP核，可直接仿真使用-DEF algorithm for FIR filter verilog code with multiplier IP core, can be directly used simulation
Platform: | Size: 2048 | Author: 右下角 | Hits:

[VHDL-FPGA-Verilog] 不用IP核设计乘法器

Description: VerilogHDL语言实现 不用IP核设计乘法器。(VerilogHDL language, do not use IP core design multiplier.)
Platform: | Size: 405504 | Author: 朱朱8 | Hits:

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