Search - Max-plus2

[Documents] EDA

Description: 60进制计数器序列检测器适用于MAX PLUS2程序开发-60 hexadecimal counter sequence detector for MAX PLUS2 development
Platform: | Size: 1024 | Author: cross | Hits:

[VHDL-FPGA-Verilog] EDA

Description: 作为大家学习参考使用！关于max plus2软件如何使用的一些详细说明，大家可以一步一步来学！很好！-U.S. study to use as a reference!
Platform: | Size: 408576 | Author: 宋露 | Hits:

[Other] judge7

Description: 实用七人表决器源码，可直接到max+plus2上验证。-Useful source of seven voting machines can be directly to the max+ plus2 to validate.
Platform: | Size: 1024 | Author: chenx | Hits:

Description: 很多初学者不知道怎么使用maxplus2，这个ppt完整并且详细的介绍了软件的功能以及使用-Many beginners do not know how to use maxplus2, this ppt complete and detailed introduction to the software functionality and the use of
Platform: | Size: 5832704 | Author: 李杜 | Hits:

[Embeded-SCM Develop] eda2

Description: 工具MAX+PLUS2，用VHDL语言实现一个三层电梯的控制。-Tool MAX+ PLUS2, with the VHDL language to achieve a three-story elevator control.
Platform: | Size: 1133568 | Author: shang | Hits:

[Embeded-SCM Develop] vhdl-szdyb

Description: 自己编写的数字电压表源代码，在MAX+PLUS2中已调试通过。-I have written the source code of the digital voltmeter, in the MAX+ PLUS2 have to debug through.
Platform: | Size: 2048 | Author: fjb | Hits:

[VHDL-FPGA-Verilog] QuadE-ResponderBasedOnVHDL

Description: 基于VHDL语言开发的四路电子抢答器，开发环境为MAX-Plus2-VHDL language development based on four electronic answering device
Platform: | Size: 92160 | Author: hmy | Hits:

[VHDL-FPGA-Verilog] hainan

Description: MAX+PLUS2环境下VHDL彩灯控制器编程 1．有十只LED，L0……L9 2．显示方式 ①先奇数灯依次灭 ②再偶数灯依次灭 ③再由L0到L9依次灭 3．显示间隔0.5S，1S可调-MAX+ PLUS2 programming environment, VHDL lantern controller 1. With 10 LED, L0 ... ... L9 2. Display odd lights turn off before ① ② ③ again even lights turn off and then turn off by the L0 to L9 3. Display interval 0.5S, 1S adjustable
Platform: | Size: 1024 | Author: 吴海霞 | Hits:

[VHDL-FPGA-Verilog] vhdl_TRAFFIC

Description: 十字路口，交通灯， VHDL ， EDA，用MAX+PLUS2运行，-Intersections, traffic lights, VHDL, EDA, with the MAX+ PLUS2 run
Platform: | Size: 5120 | Author: dongni | Hits:

[Embeded-SCM Develop] maxPplus2

Description: 本资料介绍了max+plus2软件的基本使用方法。包括新建及一些基本工具的使用。-This information describes the basic max+ plus2 software to use. Including new and some basic tools.
Platform: | Size: 267264 | Author: 涂淑荣 | Hits:

[VHDL-FPGA-Verilog] frequency-meter-of-same-precision

Description: 本系统采用了以Altera芯片EPF10K10LC84-4和单片机仿真器伟福H51/S POD-H8X5X 为核心，同时辅有8位七段数码管和7219数码管驱动芯片。设计使用max+plus2，keil3和伟福开发环境，其中FPGA计数功能，FPGA与单片机的接口通信，单片机计算数据并驱动显示模块等功能。系统实现了4hz~12Mhz频率的测量，并利用科学计数法显示。测量相对误差在0.005 以内，每个频段均显示6位有效数字。本系统的特点在于高精度，显示界面科学友好。硬件部分VHDL语言描述简洁明快，单片机C语言算法仔细精巧。关键词：等精度，频率计，FPGA,单片机 -This system USES to EPF10K10LC84-4 and Altera chip microcontroller simulators weifu H51/S POD-H8X5X as the core, and auxiliary has eight seven period of digital the and 7219 digital tube drive chip. Design the Max+ plus2, keil3 and weifu development environment, including FPGA count function, FPGA and single-chip microcomputer interface communication, single chip computer data and drive display module etc. Function. The system realizes the 4 hz ~ 12 Mhz frequency measurement, and use of scientific notation display. Measuring relative error within 0.005 , each frequency band all showed that six effective digital. This system is characterized by high precision, display interface science friendly. Hardware VHDL language description is concise and lively, SCM C language carefully algorithm is exquisite. Key words:, accuracy, the frequency meter, FPGA, microcontroller
Platform: | Size: 552960 | Author: 穆环 | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[Documents] EDA

[VHDL-FPGA-Verilog] EDA

[Other] judge7

[Other] maxplus2

[Embeded-SCM Develop] eda2

[Embeded-SCM Develop] vhdl-szdyb

[VHDL-FPGA-Verilog] QuadE-ResponderBasedOnVHDL

[VHDL-FPGA-Verilog] hainan

[VHDL-FPGA-Verilog] vhdl_TRAFFIC

[Embeded-SCM Develop] maxPplus2

[VHDL-FPGA-Verilog] frequency-meter-of-same-precision

[VHDL-FPGA-Verilog] jzjpjsq_jiajianchengchu

[VHDL-FPGA-Verilog] miaobiao

[VHDL-FPGA-Verilog] duogongnengshuzizhong

[VHDL-FPGA-Verilog] graph

[VHDL-FPGA-Verilog] dac

[Embeded-SCM Develop] vhdl-szdyb

CodeBus www.codebus.net