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[Other resource] szz

Description: 是EDA设计的数字钟的VHDL语言程序，可用Max+Plus2进行编译，仿真并下载到芯片中。
Platform: | Size: 2151 | Author: leo | Hits:

[Other] MAXPLUS2

Description: EDA课程所用的Max Plus2软件，制作的半加器，有图像文件，有波形文件，建议看看，
Platform: | Size: 31798 | Author: jimchen | Hits:

[Other resource] decoder3_to_8

Description: max-plus2 编写的3-8译码器
Platform: | Size: 55146 | Author: xiao | Hits:

[Other resource] chuan_to_bing

Description: 16位A/D转换程序，使用MAX+PLUS2做的，用状态机做的，但不够完善，望大家见谅
Platform: | Size: 901 | Author: 邓孟楠 | Hits:

[Other resource] dianzizhong

Description: Max plus2设计的电子钟 计算机iaji时间爱上佳洁士i好ikskas萨
Platform: | Size: 16217 | Author: 赵科星 | Hits:

[Software Engineering] max+plus2使用指南

Description:
Platform: | Size: 299358 | Author: hongyue1989@gmail.com | Hits:

[Other] keyboard590

Description: 基于max plus2的ahdl语言。这个是键盘扫描程序的ahdl。文件格式是tdf。可以扫描键盘。-based on the max plus2 ahdl language. This is the keyboard ahdl scanning procedures. File format is TDF. Scan the keyboard.
Platform: | Size: 1024 | Author: wenwen | Hits:

[Other] 7segment

Description: 这个是max plus2的7段数码管的扫描程序。文件格式为hif，介绍7段数码管的设计方法。 你好，管理员，我十分需要贵网站的一个程序，请为我开通下载。我会尽力上传源码，支持网站的发展。-this is the max plus2 7 of the tube digital scanning procedures. Hif document format, introduced seven of the digital control design methods. Hello, administrators, I need your web site a program, I opened for download. I will try to upload source to support the development of the website.
Platform: | Size: 1024 | Author: wenwen | Hits:

[Printing program] chuzuche

Description: 基于max+plus2的开发平台程序，比较不错 有不懂的联系我的邮箱-based on the development platform procedures are quite good, I do know that the mail links
Platform: | Size: 3072 | Author: 啊辉 | Hits:

[VHDL-FPGA-Verilog] HXRJTD

Description: 这是本人在Max plus2环境下用VHDL语言编的交通灯控制程序。做EDA课程设计的朋友可以下来参考参考。-This is my Max plus2 environment with VHDL addendum to the traffic lights control procedures. EDA design courses so friends from the reference reference.
Platform: | Size: 754688 | Author: 健 | Hits:

[Books] sj1

Description: 电子售货机的vhdl程序，用max-plus2编译，-electronic vending machines in vhdl procedures used max-plus2 compiler,
Platform: | Size: 91136 | Author: 木车 | Hits:

[VHDL-FPGA-Verilog] liangzhu

Description: 基于max—plus2开发环境，设计的《梁祝》演奏曲-based max-plus2 development environment, the design of the "Butterfly Lovers" concert song
Platform: | Size: 448512 | Author: 唐天 | Hits:

[VHDL-FPGA-Verilog] zyj

Description: 包含了电子时钟的主要功能,输入CLK为1KHZ,输出为动态扫描8段CLD显示.有闹铃,正点报时,时间调整.调整时能够闪烁显示.本时钟为24小时制.课程设计优秀通过.运行平台:MAX+PLUS2.-Contains the main function of the electronic clock, input CLK for 1KHZ, output for the dynamic scan 8 CLD show. There are alarm, on-time time, time to adjust. Adjustment can display flashes. The clock for the 24-hour clock. Curriculum design excellence through. platform: MAX+ PLUS2.
Platform: | Size: 5120 | Author: zyj | Hits:

[VHDL-FPGA-Verilog] eda

Description: 来自某名牌大学电子实验室的eda指导教程，主要介绍了maxplus2，适合初学者-From a prestigious university guide EDA Electronic lab tutorials, mainly the introduction maxplus2, suitable for beginners
Platform: | Size: 484352 | Author: xiaoshuai | Hits:

[VHDL-FPGA-Verilog] szz

Description: 是EDA设计的数字钟的VHDL语言程序，可用Max+Plus2进行编译，仿真并下载到芯片中。-EDA design is the VHDL language digital clock program that can be used Max+ Plus2 compile, simulation and downloaded to the chip.
Platform: | Size: 2048 | Author: leo | Hits:

[Other] MAXPLUS2

Description: EDA课程所用的Max Plus2软件，制作的半加器，有图像文件，有波形文件，建议看看，-EDA courses used by Max Plus2 software, produced a half-adder, there are image files, documents have waveform, it is recommended to see,
Platform: | Size: 31744 | Author: jimchen | Hits:

[VHDL-FPGA-Verilog] chuan_to_bing

Description: 16位A/D转换程序，使用MAX+PLUS2做的，用状态机做的，但不够完善，望大家见谅
Platform: | Size: 1024 | Author: 邓孟楠 | Hits:

[SCM] dianzizhong

Description: Max plus2设计的电子钟 计算机iaji时间爱上佳洁士i好ikskas萨-Max plus2 designed electronic bell computer Crest iaji time i fell in love with a good ikskas Sa
Platform: | Size: 16384 | Author: 赵科星 | Hits:

[Software Engineering] jiaotongdeng

Description: 交通灯程序,实现十字路口的交通灯控制. 使用max+plus2编写的.-Procedures for traffic lights to achieve the traffic signal controlled crossroads. Use max+ Plus2 prepared.
Platform: | Size: 188416 | Author: good | Hits:

[VHDL-FPGA-Verilog] travel

Description: 自己做的vhdl课程设计，交通灯：实现主干道倒计时，分别为30,20,5秒，分情况：当主干道有车时，红黄绿交替，当只一个道路上有车时，那个道的交通灯变绿色，利用max+plus2做成，使用flex8000,epf8282alc84_4只用加一个38译码器模块即可，使用别的板子也可以运行-VHDL to do their own curriculum design, traffic lights: the realization of the trunk road countdown, 30,20,5 seconds, respectively, sub-cases: When there are car trunk, red, yellow, and green alternately, when there is only a road car, the Road change traffic lights green, the use of max+ plus2 make, use flex8000, epf8282alc84_4 only 38 plus a decoder module can, use the other board can also run
Platform: | Size: 529408 | Author: 安治州 | Hits:
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