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Description: This document contains a specification for a new low pin count bus interface, dubbed LPC, that will be added to
future Intel chip-sets. The target audience for this document are system and component designers.
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Size: 934677 |
Author: 李俊 |
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Description: lpc源代码verilog实现的。操作low pin count设备
Platform: |
Size: 1604 |
Author: 毛军捷 |
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Description: This document contains a specification for a new low pin count bus interface, dubbed LPC, that will be added to
future Intel chip-sets. The target audience for this document are system and component designers.
Platform: |
Size: 934912 |
Author: 李俊 |
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Description: lpc源代码verilog实现的。操作low pin count设备-LPC realize the Verilog source code. Operation of low pin count devices
Platform: |
Size: 1024 |
Author: 毛军捷 |
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Description: LPC总线从设备的verilog设计,包含状态机和中断功能。-verilog code for LPC device
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Size: 5120 |
Author: 饶进平 |
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Description: Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided.
None of this has been tested (yet) with a third-party LPC Peripheral or Host.
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Size: 410624 |
Author: Arun |
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Description: Low Pin Count Interface Specification, Revision 1.1 (LPC)
Platform: |
Size: 380928 |
Author: 张恒 |
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Description: This document contains a specification for a new low pin count bus interface, called LPC. The
target audiences for this document are system and component designers.
Platform: |
Size: 24576 |
Author: sungd |
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Description: LPC标准 V1.1.PDF
Low Pin Count V1.1.PDF-Low Pin Count V1.1.PDF
Platform: |
Size: 380928 |
Author: 吴俊泉 |
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