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Description: 功能是测试本地机子的L1 data和L2 data cache的大小-Function is to test the local machine of L1 data and L2 data cache size
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Size: 10240 |
Author: 林帅 |
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Description: 使用C++语言编写程序测量实际机器的数据Cache大小与结构。
1.使用程序自动测量目标机的L1 Data Cache 与L2 Data Cache的大小（最低要求）
2.测量各级D-Cache的块大小,相连度（一般要求）
3.测量Cache write back/write through, 替换策略-The use of C++ Language programming measurement of the actual machine data Cache size and structure. 1. The use of procedures for automatic measurement of the target machine L1 Data Cache and L2 Data Cache size (minimum requirements) 2. Measured levels of D-Cache block size, connected degrees (general requirements) 3. Measuring Cache write back/write through, Replacement Strategy
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Size: 124928 |
Author: Draco |
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Description: 介绍C64xx DSP Cache的资料，帮助你理解L1，l2的区别-C64xx DSP Cache introductory information to help you understand the L1, l2 distinction
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Size: 186368 |
Author: 陈利聪 |
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Description: The purpose of this project is to explore the issues and implementation of a multiple instruction stream, single data stream processor. We are running two instruction streams on two CPUs which share an address space. The processors share a second level cache, and maintain coherence at the L1 cache with a write-invalidate policy. The L2 cache is two-way set associative, with a block size of 8 words, and a total capacity of 512 words.
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Size: 299008 |
Author: sandeep |
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Description: It is a cache simulator for L1 and L2
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Size: 1024 |
Author: Hassan |
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Description: 测量IA32体系cpu中 L2 miss次数的动态库 和 头文件及源代码，适合于研究系统性能研究人员-The dynamic lib is used to get the counter value of L2 miss in IA32 cpu.
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Size: 39936 |
Author: zwb |
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Description: * This example demonstrates how to switch L2 CACHE mode at run-time.
-* This example demonstrates how to switch L2 CACHE mode at run-time.
Platform: |
Size: 2048 |
Author: Sunny |
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Description: Samsung s new ARM cpu datasheet. S5PC100
Spec.
- CPU ARM Cortex-A8 667-833Mhz
- 32KB L1, 256KB L2 Cache
- Video 720p (1280x720 Play. h.264 divx, mp4...)
- nand, sd/mmc, usb booting
- Windows CE 6.0, Linux (*Android) support
- support 166MHz memory clock. DDR, mobileDDR, DDR2
* in actually, i run c100 board ddr2 bus clock at 280MHz in WinCE 6.0
Platform: |
Size: 12115968 |
Author: john |
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Description: VS 2008上，测试通过，能过获取CPU的一级数据缓存，以及指令缓存，二级缓存，三级缓存-L1 Data Cache, L2 Cache, L3 Cache
Platform: |
Size: 2368512 |
Author: xiejjsss |
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Description: L2 cache 文档，用于ARM1136-l2 cache for arm1136
Platform: |
Size: 711680 |
Author: tangjiayue |
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Description: 获取CPU一级二级缓存大小
L1 Cache L2Cache-Get CPU L1/L2 cache size
(L1 Cache L2Cache)
Platform: |
Size: 39936 |
Author: Jim |
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Description: Feroceon L2 cache controller support driver for Linux.
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Size: 3072 |
Author: ringjanbin |
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Description: Tauros2 L2 cache controller support driver for Linux.
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Size: 2048 |
Author: guikieji |
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Description: Feroceon L2 cache controller support.
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Size: 2048 |
Author: cangcengsin |
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Description: Tauros2 L2 cache controller support for Linux v2.13.6.
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Size: 3072 |
Author: pbfxpp |
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Description: l2 cache initialization for CSR SiRFprimaII.
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Size: 4096 |
Author: vlgiegi |
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Description: Flush and disable all data caches (dL1, L2, L3.
Platform: |
Size: 4096 |
Author: mwdepe |
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Description: Tauros2 L2 cache controller support.
Platform: |
Size: 3072 |
Author: jingzvring |
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Description: BCM1280 BCM1480 Board Support Package L2 Cache constants and macros.
-BCM1280 BCM1480 Board Support Package L2 Cache constants and macros.
Platform: |
Size: 2048 |
Author: yjciejin |
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Description: The aux_val and aux_mask have no effect since L2 cache is already enabled. Pass 0s for aux_val and 1s for aux_mask for default value.
Platform: |
Size: 8192 |
Author: hiusrmou |
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