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Description: 高质量的VHDL代码乒乓处理FIFO缓存-High-quality VHDL code deal with ping-pong FIFO cache
Platform: |
Size: 1024 |
Author: wode |
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Description: 用双端口ram实现异步fifo，采用格雷码，避免产生毛刺。-Using dual-port ram realize asynchronous fifo, the use of Gray code, avoiding the production of burr.
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Size: 1024 |
Author: shili |
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Description: para13：
fifo.vhd FIFO（双口RAM）
fifo1.vhd FIFO（嵌入式EAB）
fifo2.vhd FIFO（LPM）-para13: fifo.vhd FIFO (dual port RAM) fifo1.vhd FIFO (embedded EAB) fifo2.vhd FIFO (LPM)
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Size: 3072 |
Author: libing |
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Description: 512×8bid的FIFO 含工程文件，基于QUARTUs-512 × 8bid the FIFO with the project document, based on the QUARTUsII
Platform: |
Size: 4096 |
Author: 邵捷 |
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Description: This a FIFO in VHDL Code-This is a FIFO in VHDL Code
Platform: |
Size: 3072 |
Author: lagartojj |
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Description: FIFO设计的参考文档
Project name : Fifo
-- Project description : Fifo controller Unit
工程名 : FIFO.VHD
用到库文件IEEE.STD_LOGIC_1164-FIFO reference design document
Project name : Fifo
-- Project description : Fifo controller Unit
--
-- File name : FIFO.VHD
-- Destination library :
-- Dependencies : IEEE.STD_LOGIC_1164
Platform: |
Size: 2048 |
Author: mhb |
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Description: 此为基于Xilinx的FPGA用VHDL实现的FIFO，已调通，可直接运行。-This is based on Xilinx FPGA using VHDL implementation of the FIFO, has been transferred through, can be directly run.
Platform: |
Size: 287744 |
Author: fafa |
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Description: ad9910 DDS板 VHDL源代码，在Cyclone II FPGA上调试通过，主要文件说明：
Filename Function
-----------------------------------------------------
dds_controller.vhd top entity, opcode decoding
ddslib.vhd configuration,opcode definition
dds_serial.vhd parallel to serial decoding
fifo.vhd FIFO megafunction intance
phase_register.vhd phase registers
-ad9910 DDS board VHDL source code, in the Cyclone II FPGA debugging through the main file description: Filename Function----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration, opcode definition dds_serial.vhd parallel to serial decoding fifo.vhd FIFO megafunction intance phase_register.vhd phase registers-----------------------------------------------------
Platform: |
Size: 93184 |
Author: bin |
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Description: Async. FIFO for rtl coding and simulation
Platform: |
Size: 2048 |
Author: akurnya |
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Description: 异步FIFO VHDL代码实现，包括：async_fifo_show_ahead.vhd，
async_fifo_show_ahead_rd_task_logic.vhd，async_fifo_show_ahead_wr_task_logic.vhd，
sync_r2w.vhd，sync_ram_std_dc.vhd，sync_w2r.vhd-The asynchronous FIFO VHDL code implementation, including: async_fifo_show_ahead.vhd, async_fifo_show_ahead_rd_task_logic.vhd, async_fifo_show_ahead_wr_task_logic.vhd, sync_r2w.vhd, sync_ram_std_dc.vhd, sync_w2r.vhd
Platform: |
Size: 7168 |
Author: taxi |
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Description: VHDL实现FIFO，模块化，可以直接使用。
Platform: |
Size: 1916 |
Author: 1269197367@qq.com |
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Description: fifo
Integrated Broadband Electronics
Platform: |
Size: 2048 |
Author: Mufossa |
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