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[Other resourceDaFilter

Description: /* This program generates the DApkg.vhd file that is used to define * the DA filter core and gives its parameters and the contents of the * Distributed Arithmetic Look-up-table \"DALUT\" according to the DA algorithm-/ * This program generates the DApkg.vhd fi le that is used to define the DA * filter core and g ives its parameters and the contents of the Dis * tributed Arithmetic Look-up-table "DALUT" ac cording to the DA algorithm
Platform: | Size: 15595 | Author: 陈朋 | Hits:

[Other resourcemdct.tar

Description: 这是06年4月刚刚完成的程序,从opencore.org下载而来。用vhdl语言描写,以及matlab仿真,testbench,以及在xinlinx上的综合。 The MDCT core is two dimensional discrete cosine transform implementation designed for use in compression systems like JPEG. Architecture is based on parallel distributed arithmetic with butterfly computation. -This is April 06 had just completed the process, from opencore.org downloaded from. Vhdl description language used, and Matlab simulation, testbench, and the Comprehensive xinlinx. The MDCT core is two dimensional discrete cosin e transform implementation designed for use in JPEG compression systems like. Architecture i 's based on parallel distributed arithmetic wit h butterfly computation.
Platform: | Size: 1767014 | Author: 陈朋 | Hits:

[VHDL-FPGA-VerilogDaFilter

Description: /* This program generates the DApkg.vhd file that is used to define * the DA filter core and gives its parameters and the contents of the * Distributed Arithmetic Look-up-table "DALUT" according to the DA algorithm-/* This program generates the DApkg.vhd fi le that is used to define the DA* filter core and g ives its parameters and the contents of the Dis* tributed Arithmetic Look-up-table "DALUT" ac cording to the DA algorithm
Platform: | Size: 15360 | Author: 陈朋 | Hits:

[VHDL-FPGA-Verilogmdct.tar

Description: 这是06年4月刚刚完成的程序,从opencore.org下载而来。用vhdl语言描写,以及matlab仿真,testbench,以及在xinlinx上的综合。 The MDCT core is two dimensional discrete cosine transform implementation designed for use in compression systems like JPEG. Architecture is based on parallel distributed arithmetic with butterfly computation. -This is April 06 had just completed the process, from opencore.org downloaded from. Vhdl description language used, and Matlab simulation, testbench, and the Comprehensive xinlinx. The MDCT core is two dimensional discrete cosin e transform implementation designed for use in JPEG compression systems like. Architecture i 's based on parallel distributed arithmetic wit h butterfly computation.
Platform: | Size: 1767424 | Author: 陈朋 | Hits:

[Multimedia programjpeg-ari-28mar98.tar

Description: A back-end implemenation of arithmetic coding for JPEG as defined in the standard. It is distributed as an add-on that can be used with the Independent JPEG groups library. The work of Guido Vollbeding.-A back-end co implemenation of arithmetic ding for JPEG as defined in the standard. It is di stributed as an add-on that can be used with the I ndependent groups JPEG library. The work of Gui Vollbeding do.
Platform: | Size: 47104 | Author: Foxxing | Hits:

[VHDL-FPGA-VerilogFIR

Description: FIR数字滤波器分布式算法的原理及FPGA实现-Distributed Arithmetic FIR digital filter FPGA Principle and realize
Platform: | Size: 599040 | Author: 王杰 | Hits:

[VHDL-FPGA-Verilog6tapFIR

Description: 6阶FIR+verliog+分布式算法(DA)-6 bands FIR+ Verliog+ Distributed Arithmetic (DA)
Platform: | Size: 2048 | Author: zs | Hits:

[OtherDA

Description: [PDF]Applications of Distributed Arithmetic to Digital Signal Processing: A Tutorial Review
Platform: | Size: 180224 | Author: Victor | Hits:

[Mathimatics-Numerical algorithmsDA

Description: distributed arithmetic
Platform: | Size: 184320 | Author: Vampiro | Hits:

[OtherDistributedArithmeticinFPGA

Description: distributed arithmetic
Platform: | Size: 114688 | Author: jai | Hits:

[VHDL-FPGA-VerilogDA_orginal

Description: simple example of how Distributed Arithmetic works-simple example of how Distributed Arithmetic works
Platform: | Size: 83968 | Author: Ali | Hits:

[Mathimatics-Numerical algorithmsDA

Description: This file contains some basics of Distributed arithmetic
Platform: | Size: 153600 | Author: Mohamed Ibrahim | Hits:

[Program docDA-500-600

Description: Distributed arithmetic used for multiplier-less FIR filter implementation to reduce the computational complexity.
Platform: | Size: 93184 | Author: sakhi | Hits:

[Software EngineeringFIR-DA-2

Description: This is distributed arithmetic algorithm
Platform: | Size: 7168 | Author: prabha | Hits:

[Otherda_fir

Description: 基于FPGA分布式算法FIR滤波器verilog代码 (本人 小论文 代码,通过验证) ​ 本文提出一种新的FIR滤波器FPGA实现方法。讨论了分布式算法原理,并提出了基于分布式算法FIR滤波器的实现方法。通过改进型分布式算法结构减少硬件资源消耗,用流水线技术提高运算速度,采用分割查找表方法减小存储规模,并在Matlab和Modelsim仿真平台得到验证。​ 为了节省FPGA逻辑资源、提高系统速度,设计中引入了分布式算法实现有限脉冲响应滤波器(Finite Impulse Response, FIR)。由于FIR滤波器在实现上主要是完成乘累加MAC的功能,采用传统MAC算法设计FIR滤波器将消耗大量硬件资源。而采用分布式算法 (Distributed Arithmetic, DA),将MAC运算转化为查找表(Look-Up-Table, LUT)输出,不仅能在硬件规模上得到改善,而且更易通过实现流水线设计来提高速度。因此本文采用分布式算法设计一个可配置的FIR滤波器,并以31阶的低通FIR滤波器为例说明分布式算法滤波器结构。- FPGA verilog
Platform: | Size: 6144 | Author: 石康 | Hits:

[VHDL-FPGA-VerilogCoreFIR_RTL-3.0

Description: actelIP核 的fircore Core Generator – Executable File Outputs Run-Time Library (RTL) Code and Testbench Based on Input Parameters – Self-Checking – Executable Tests Generated Output against Algorithm • Distributed Arithmetic (DA) Algorithm – Multiplier-Free Computation – Low Cost – Optimized for Actel FPGAs • Folding Architecture to Minimize Design Size – Serialized Computation when System Clock Rate is Faster than the Data Sample Rate • Efficient Structure Using Embedded RAMs – Lookup Tables Utilize Embedded RAMs • On-Chip DA Lookup Table Generator for FPGA with Embedded RAMs • Embedded RAMs Initialized as DA Lookup Table • DA Lookup Table ROM Synthesis for FPGA without Embedded RAMs • Multiple DA lookup Tables to Split Large Number of Taps • Actel FPGA-Optimized RTL Code • Supports 2 to 128 Taps • 1- to 32-Bit Input Data and Coefficient Precision-actelIPcore fircore Core Generator – Executable File Outputs Run-Time Library (RTL) Code and Testbench Based on Input Parameters – Self-Checking – Executable Tests Generated Output against Algorithm • Distributed Arithmetic (DA) Algorithm – Multiplier-Free Computation – Low Cost – Optimized for Actel FPGAs • Folding Architecture to Minimize Design Size – Serialized Computation when System Clock Rate is Faster than the Data Sample Rate • Efficient Structure Using Embedded RAMs – Lookup Tables Utilize Embedded RAMs • On-Chip DA Lookup Table Generator for FPGA with Embedded RAMs • Embedded RAMs Initialized as DA Lookup Table • DA Lookup Table ROM Synthesis for FPGA without Embedded RAMs • Multiple DA lookup Tables to Split Large Number of Taps • Actel FPGA-Optimized RTL Code • Supports 2 to 128 Taps • 1- to 32-Bit Input Data and Coefficient Precision
Platform: | Size: 1051648 | Author: 睿宸 | Hits:

[Industry researchdocs

Description: papers based on distributed arithmetic.
Platform: | Size: 11536384 | Author: arka | Hits:

[matlabFIRdigitalfilter

Description: digital filter implementation through ROM modelling and distributed arithmetic
Platform: | Size: 1024 | Author: kaustubh | Hits:

[OtherDistributed-Arithmetic

Description: ppt overview of distrubuted arithmetic fir filter implementation by vhdl
Platform: | Size: 169984 | Author: Dwarakanadh | Hits:

[OtherA memory and area‑efficient distributed arithmetic based modular VLSI architecture of 1D/2D reconfigurable 9/7 and 5/3 D

Description: In this article, we have proposed the internal architecture of a dedicated hardware for 1D/2D convolution-based 9/7 and 5/3 DWT filters, exploiting bit-parallel ‘distributed arithmetic’ (DA) to reduce the computation time of our proposed DWT design while retaining the area at a comparable level to other recent existing designs. Despite using memory extensive bitparallel DA, we have successfully achieved 90% reduction in the memory size than that of the other notable architectures. Through our proposed architecture, both the 9/7 and 5/3 DWT filters can be realized with a selection input, mode. With the introduction of DA, we have incorporated pipelining and parallelism into our proposed convolution-based 1D/2D DWT architectures. We have reduced the area by 38.3% and memory requirement by 90% than that of the latest remarkable designs. The critical-path delay of our design is almost 50% than that of the other latest designs. We have successfully applied our prototype 2D design for real-time image decomposition. The quality of the architecture in case of real-time image decomposition is measured by ‘peak signal-to-noise ratio’ and ‘computation time’, where our proposed design outperforms other similar kind of software- and hardware-based implementations.
Platform: | Size: 3442321 | Author: nalevihtkas | Hits:
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