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[VHDL-FPGA-Verilog] division

Description: 很实用的一个分频带码，包括奇分频，偶分频，占空比为50％的奇分频,实际工程中很实用-Very useful to a sub-band code, including the odd sub-frequency, dual frequency, duty cycle 50 of the odd sub-frequency, the actual works in very practical
Platform: | Size: 290816 | Author: ecomputer | Hits:

[VHDL-FPGA-Verilog] fenpin

Description: 分频电路的研究 主要包括：偶数分频（二分频、偶数分频占空比50 ）、奇数分频（占空比50 、占空比非50 ）、半整数分频（不要求占空比）、小数分频（不要求占空比）。 -Frequency of the circuit includes: an even frequency (half frequency, frequency 50 duty cycle even), odd-frequency (50 duty cycle, duty cycle of non-50 ), half-integer frequency division (not required duty cycle), fractional (not required duty cycle).
Platform: | Size: 16384 | Author: lishaohui | Hits:

[VHDL-FPGA-Verilog] fenpin-FPGA

Description: 本文通过在QuartursⅡ开发平台下，一种能够实现等占空比、非等占空比整数分频及半整数分频的通用分频器的FPGA设计与实现，介绍了利用VHDL硬件描述语言输入方式，设计数字电路的过程。-In this paper, the development platform in Quarturs Ⅱ, one can achieve such duty, such as the duty cycle of non-integer frequency division and semi-integer frequency divider of the FPGA general-purpose design and implementation, describes the use of VHDL hardware description language input , digital circuit design process.
Platform: | Size: 17408 | Author: liu | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: FPGA 时钟分频器，包括偶数分频和奇数分频两种，本程序占空比为50-FPGA clock divider, including even and odd frequency division two, 50 duty cycle of the program
Platform: | Size: 2048 | Author: chenquan | Hits:

[SCM] Ultrasonic-display-LCD1602

Description: 調試要求： 1.MCU:AT89S52芯片或AT89C52 2.晶振:12MHz 調試注意： 本程序不帶溫度補償 1.LCD1602液晶屏有顯示後，才接入超聲波模塊。 2.注意超聲波模塊電源的極性。不清楚請參好淘寶的電路圖 3.沒有選用頻率為12MHz晶振，用了別的頻率晶振,單片機定時器的測量值與發出的40KHz頻率脈衝不對。 4.使用者經常誤發出20KHZ脈衝當40KHZ脈衝。（40KHz頻率脈衝，週期25us,占空比為50 = 12.5us） 5.如果是用開發板調超聲波模塊,請檢查開發板上的電路是否與超聲波模塊的 控制腳復用了, 若復用了,請通過跳線分開發板上的電路。 6.如果使用的是萬用板，請確定單片機的復位電路和晶振電路是否正常，同時單片機的31腳（EA）記得 接高電平。-The debugging requirements: 1.MCU: AT89S52 chip AT89C52 2. Crystal: 12MHz debugging Note: the program without the temperature compensation 1.LCD1602 LCD display access ultrasonic module. Note ultrasonic module power supply polarity. Unclear please refer to the a good Taobao circuit diagram 3. Chosen frequency 12MHz crystal oscillator with a different frequency crystal, the microcontroller timer measurement values ​ ​ with the issue 40KHz frequency pulse is not right. Users often mistakenly issued 20KHZ pulse when 40KHZ pulse. (40KHz frequency pulse, cycle 25us, a duty cycle of 50 = 12.5us), 5. Tune with development board ultrasonic module, please check the development board circuit with the the ultrasonic module control pin multiplexing, Ruofu by jumper division developed the circuit board. 6 If you are using a wildcard board, to determine whether the microcontroller reset circuit and crystal oscillator circuit, microcontroller 31 feet (EA) remember to connect the high level
Platform: | Size: 37888 | Author: Poter | Hits:

[Software Engineering] SVPWM

Description: 为了避免复杂的三角函数和求根运算，便于数字信号处理器的实时运算，提出一种新 的SVPWM算法。采用SPWM中调制波与载波相比较的规则采样思路，通过在静止坐标系下直接 计算每个参考电压矢量所对应的三相调制波的函数值，进而得到每相电压在一个PWM周期中的 占空比．该算法的主要特点是计算简单，只需要普通的四则运算，适用于数字化系统。在扇区划 分和占空比饱和的处理上较传统SVPWM算法更简便，且过调制范围也略有拓展，具有很大的实 用性。仿真和实验结果证实了该算法的有效性。-In order to avoid complex trigonometric and root operation, ease of operation, real-time digital signal processor, propose a new SVPWM algorithm. Using SPWM modulation wave in comparison with the carrier' s regular sampling ideas, through the stationary coordinate system directly calculated for each reference voltage vector corresponding to the phase modulation wave function value, and then get each phase voltage in a PWM period accounted for air ratio. The main features of the algorithm is to calculate simple and requires only ordinary arithmetic for digital systems. Saturation in the sector division and duty cycle of the treatment more convenient than traditional SVPWM algorithm, and also a slight over-modulation range expansion, with great practicality. Simulation and experimental results confirm the effectiveness of the algorithm.
Platform: | Size: 455680 | Author: shitou | Hits:

[VHDL-FPGA-Verilog] fenpin

Description: 分频程序，偶数分频，奇数分频，占空比可调，小数分频-Dividing frequency division program, even, odd points frequency, duty cycle adjustable, the decimal frequency division
Platform: | Size: 1024 | Author: 高飞 | Hits:

[VHDL-FPGA-Verilog] Clock_div

Description: 偶数分频及50占空比输出，很详细，适合初学者-Even frequency division and duty cycle of the output 50, in great detail, suitable for beginners
Platform: | Size: 1024 | Author: 辛书伟 | Hits:

[VHDL-FPGA-Verilog] fenpin

Description: 基于50M分10K 1K 1000 100 10 1的分频，占空比 10/1-Based 50M min 10K 1K 1000 100 10 1 division, duty cycle 10/100
Platform: | Size: 1024 | Author: 辛书伟 | Hits:

[VHDL-FPGA-Verilog] diver

Description: 根据芯片的始终频率进行分频，可调节占空比。容易实现。(The frequency division is carried out according to the chip frequency at all times, and the duty cycle is adjusted. Easy to implement.)
Platform: | Size: 3076096 | Author: 紫芩 | Hits:

[VHDL-FPGA-Verilog] fenpin51

Description: 任意整数分频器，输出方波可调占空比（已仿真下板子验证）第一个系数为分频系数，第二个为高电平所占整个方波的比例(Arbitrary integer frequency divider, output square wave adjustable duty cycle (has been simulated under board verification), the first factor for the frequency division coefficient, the second for the high level, the proportion of the whole square wave)
Platform: | Size: 63488 | Author: 奋斗小二逼 | Hits:

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