Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - DCT hdl

Search list

[Other resource] 20060412183015974

Description: 是关于dct的Verilog HDL源代码和测试程序-on the Verilog HDL source code and testing procedures
Platform: | Size: 31498 | Author: 凌风 | Hits:

[Other resource] Dct_verilog

Description: 采用verilog hdl 语言实现整形dct算法，设计合理，算法简单，是红色逻辑开发板试验程序，值得一看。
Platform: | Size: 4640 | Author: panyouyu | Hits:

[OpenGL program] DCT

Description: 用Verilog HDL编写的离散余弦变换，可用于视频图像压缩，并在modelsim SE6.0中仿真通过
Platform: | Size: 1388 | Author: yangyanwen | Hits:

[SourceCode] DCT实现Verilog HDL的数字图像处理源代码

Description: DCT实现Verilog HDL的数字图像处理
Platform: | Size: 31657 | Author: juyong | Hits:

[VHDL-FPGA-Verilog] 20060412183015974

Description: 是关于dct的Verilog HDL源代码和测试程序-on the Verilog HDL source code and testing procedures
Platform: | Size: 30720 | Author: 凌风 | Hits:

[VHDL-FPGA-Verilog] Dct_verilog

Description: 采用verilog hdl 语言实现整形dct算法，设计合理，算法简单，是红色逻辑开发板试验程序，值得一看。-Verilog hdl language used plastic realize DCT algorithm, rational design algorithm is simple and logical development board is red test procedures, worth a visit.
Platform: | Size: 4096 | Author: panyouyu | Hits:

[OpenGL program] DCT

Description: 用Verilog HDL编写的离散余弦变换，可用于视频图像压缩，并在modelsim SE6.0中仿真通过-Verilog HDL prepared with discrete cosine transform can be used for video image compression, and modelsim SE6.0 simulation through
Platform: | Size: 1024 | Author: yangyanwen | Hits:

[VHDL-FPGA-Verilog] DCT_IDCT

Description: 离散余弦变换及反离散余弦变换的HDL代码及测试文件。包括VHDL及Verilog版本。可用途JPEG及MEPG压缩算法。-Discrete cosine transform and inverse discrete cosine transform of the HDL code and test files. Including VHDL and Verilog versions. And MEPG can use JPEG compression algorithm.
Platform: | Size: 29696 | Author: caesar | Hits:

[VHDL-FPGA-Verilog] yiweiDCTbianhuan

Description: 一维DCT变换的Verilog HDL源程序，在ISE中已经通过编译，可以参考里面的文档。-One-dimensional DCT transform Verilog HDL source code, in the ISE has been through the compilation, you can refer to inside the document.
Platform: | Size: 421888 | Author: 匡匡 | Hits:

[VHDL-FPGA-Verilog] Chapter6-9

Description: 第六章到第九章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter VI to Chapter IX of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 6281216 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] verilogdct

Description: dct实现verilog hdl的数字图像处理，源代码-dct achieve verilog hdl digital image processing, source code
Platform: | Size: 28672 | Author: xutongxue | Hits:

[VHDL-FPGA-Verilog] dct

Description: all ok...4 Dec 2009 ... In this method the 2-Dimensional DCT is obtained by taking two ... column-wise 1D DCT is ascertained which gives the 2D DCT of the data. ... The design is done in Verilog HDL and the simulation is done in Modelsim 6.3b.
Platform: | Size: 1024 | Author: haziq36 | Hits:

[VHDL-FPGA-Verilog] OneD_DCT8

Description: 一维DCT变换，使用Verilog ＨＤＬ语言实现。有ＳＹｎｐｌｉｆｙ编译脚本-One-dimensional DCT, using the Verilog HDL language to achieve. The SYnplify compiled script
Platform: | Size: 2048 | Author: 海峰 | Hits:

[Wavelet] oc_mkjpeg_v63

Description: 离散DCT变换的Veilog HDL语言实现，RTL描述方式，并附有输入测试信号的testBeach文件-Discrete DCT transform Veilog HDL language, RTL description, together with the input test signal testBeach file
Platform: | Size: 1214464 | Author: 曾柯益 | Hits:

[VHDL-FPGA-Verilog] INT_DCT

Description: Verilog HDL语言实现的整数DCT变换模块。其中包括一维和两维的DCT变换模块各一个。该模块都通过硬件仿真以及FPGA实现后的测试，均满足预期的DCT变换功能。-Integer DCT transfer module with Verilog HDL format. The package includes one 1-D and one 2-D DCT transfer module, which all pass simulation and FPGA evaluation.
Platform: | Size: 2048 | Author: Alex Liu | Hits:

[Graph program] DCT

Description: 用Verilog HDL编写的离散余弦变换，可用于视频图像压缩，并在modelsim SE6.0中仿真通过-Verilog HDL prepared with discrete cosine transform can be used for video image compression, and modelsim SE6.0 simulation through
Platform: | Size: 1024 | Author: shi17395 | Hits:

CodeBus www.codebus.net