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[VHDL-FPGA-Verilog] CRC

Description: 一個CRC-12計算的串入式電路並下載至FPGA電路板-FPGA CRC-16
Platform: | Size: 1024 | Author: TAE | Hits:

[SCM] CRC8-16

Description: CRC校验的相关原理以及CRC-8和CRC-16的C语言实现。-The relevant principles of the CRC and the CRC-8 and CRC-16 of the C language.
Platform: | Size: 62464 | Author: 刘世生 | Hits:

[Communication] labview-Modbus-CRC

Description: 16位CRC校验算法，作为子VI可直接调用-16-bit CRC checksum algorithm, can be directly invoked as a sub-VI
Platform: | Size: 6144 | Author: zz | Hits:

[Mathimatics-Numerical algorithms] CRC-16

Description: 16位CRC校验原理与算法分析，不讨论CRC的纠错原理以及为什么要选下面提及的生成多项式，只是针对以下的生成多项式，如何获得CRC校验码，作一个比较详细的说明。-16-bit CRC checksum algorithm theory and analysis, not to discuss the principles of the CRC error correction, and why to choose the generator polynomial mentioned below, only for the following generator polynomial, to obtain a CRC for a more detailed instructions.
Platform: | Size: 2048 | Author: 李楠 | Hits:

[VHDL-FPGA-Verilog] Perl_for_CRC

Description: Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redundancy Check standards are CRC-8, CRC-12, CRC-16, CRC-32, and CRC-CCIT. This application note discusses the implementation of an IEEE 802.3 CRC in a Virtex™ device. The reference design provided with this application note provides Verilog point solutions for CRC-8, CRC-12, CRC-16, and CRC-32. The Perl script (crcgen.pl) used to generate this code is also included. The script generates Verilog source for CRC circuitry of any width (8, 12, 16, 32), any polynomial, and any data input width.-Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redundancy Check standards are CRC-8, CRC-12, CRC-16, CRC-32, and CRC-CCIT. This application note discusses the implementation of an IEEE 802.3 CRC in a Virtex ™ device. The reference design provided with this application note provides Verilog point solutions for CRC-8 , CRC-12, CRC-16, and CRC-32. The Perl script (crcgen.pl) used to generate this code is also included. The script generates Verilog source for CRC circuitry of any width (8, 12, 16, 32 ), any polynomial, and any data input width.
Platform: | Size: 90112 | Author: 尤恺元 | Hits:

[Program doc] CRC-algorithm-design

Description: 数字通信系统的数据传输为了保证数据传输的有效性 ,常用的方法就是对传输数据进行 CRC校验。首先分析了CRC的校验原理 ,然后以常见的CRC-16为例 ,提出了生成CRC码的算法 ,给出了该算法的实现软件流程图 ,并在Windows平台上用 VC++实现。该算法实现简单 ,实时性强 ,非常适合于大数据块传输的情况。计算机仿真实验表明 ,这是一种有效地实现CRC校验码的方法 ,为通信系统的差错控制提供了一种简捷的解决方案。-Digital communication system of data transmission in order to ensure the validity of the data transmission, the commonly used method for data transmission is the CRC check. First analysis of the CRC check of principle, and then, with common CRC-16 as an example, this paper proposes the CRC code generation algorithm was presented, the software flow chart of the realization of the algorithm, and the Windows platform with vc++ realized. The algorithm is simple, good real-time, which is very suitable for large blocks of data transmission. Computer simulation experiments show that this is a kind of effectively achieve the CRC check code method, as the communication system error control provides a simple solution.
Platform: | Size: 289792 | Author: jinzhi | Hits:

[SCM] crc

Description: 用汇编语言实现的CRC-8和CRC-16的算法包 -Calculate CRC-8 & CRC-16 Values
Platform: | Size: 6144 | Author: zentoku | Hits:

[VHDL-FPGA-Verilog] CRC.C

Description: 下面以最常用的CRC-16为例来说明其生成过程。 　　CRC-16码由两个字节构成，在开始时CRC寄存器的每一位都预置为1，然后把CRC寄存器与8-bit的数据进行异或(异或：二进制运算 相同为0，不同为1；0^0=0 0^1=1 1^0=1 1^1=0)， 　　之后对CRC寄存器从高到低进行移位，在最高位（MSB）的位置补零，而最低位（LSB，移位后已经被移出CRC寄存器）如果为1，则把寄存器与预定义的多项式码进行异或，否则如果LSB为零，则无需进行异或。重复上述的由高至低的移位8次，第一个8-bit数据处理完毕，用此时CRC寄存器的值与下一个8-bit数据异或并进行如前一个数据似的8次移位。所有的字符处理完成后CRC寄存器内的值即为最终的CRC值。 -Below the most commonly used CRC-16 as an example to illustrate the generation process. CRC-16 yards by two-bytes at the beginning of every one of the CRC register is preset to 1, then the CRC register with the 8-bit data XOR (exclusive or: the same as the binary operation 0, different 1 0 ^ 0 = 0 0 ^ 1 = 1 1 ^ 0 = 1 1 ^ 1 = 0), After the shift the CRC register from highest to lowest, the most significant bit (MSB) position zeros, the least significant bit (LSB after the shift has been out of the CRC register) 1, put the register with pre-defined item code different, or, otherwise, if the LSB is zero, you do not need to XOR. Repeat the above the descending order of the shift eight times, the first 8-bit data processing is completed, such as previous data like 8 times shift the CRC register values ​ ​ and the next 8-bit data XOR and . After completion of all the characters deal with the value of the CRC register is the final CRC value.
Platform: | Size: 11264 | Author: malimin | Hits:

[Delphi VCL] CRC32-16

Description: 输入16进制字符串即可进行CRC的16位校验和32位检验，已测试-Hexadecimal string to the CRC 16 checksum 32 test has been tested
Platform: | Size: 181248 | Author: jiecai | Hits:

[CA auth] crc

Description: Code to find CRC 16 of a sequence
Platform: | Size: 1024 | Author: Pramod | Hits:

[Algorithm] CRC-16

Description: CRC16查表式校验算法，CRC16Table为CRC表格数据，占用256个字节，使用时把此表放在ROM中-CRC16 look-up table-checksum algorithm, CRC16Table CRC tabular data, occupies 256 bytes, use this table in ROM
Platform: | Size: 5120 | Author: 陈志浩 | Hits:

[Other] MB-CRC-16

Description: modbus通信协议校crc验码,通讯控制必备哦-Modbus communication protocol school CRC check code, communication and control must Oh
Platform: | Size: 7168 | Author: 王平静 | Hits:

[matlab] crc

Description: CRC-16 编码在DECT中的应用及性能-CRC-16 encoded in the DECT Application and performance
Platform: | Size: 11264 | Author: 李宏豆 | Hits:

[LabView] CRC-16

Description: 实现PLC通讯中CRC循环冗余校验，在串口通讯过程中校验环节必不可少。-complete the function for communication between the PLC and PC
Platform: | Size: 8192 | Author: 张伊山 | Hits:

[VHDL-FPGA-Verilog] CRC

Description: CRC校验参考设计Verilog代码,crc8,16,32bit- crc8_8.v : CRC-8, 8-bit data input. crc12_4.v : CRC-12, 4-bit data input. crc16_8.v : CRC-16, 8-bit data input. crc_ccit_8.v : CRC-CCIT, 8-bit data input. crc32_8.v : CRC-32, 8-bit data input.
Platform: | Size: 10240 | Author: guangngqiang | Hits:

[VHDL-FPGA-Verilog] fast-crc.tar

Description: crc-16-code for check redundancy code fast in 16 bit- in parallel and serial architecture-crc-16-code for check redundancy code fast in 16 bit- in parallel and serial architecture
Platform: | Size: 4768768 | Author: fghj | Hits:

[LabView] CRC-16

Description: CRC Calculator，可以直接使用，也可以直接调用-CRC Calculator
Platform: | Size: 8192 | Author: 许卫平 | Hits:

[Internet-Network] CRC-code

Description: 用模2除法计算CRC码，生成多项式为CRC-16；允许输入字符等，有完备的报错功能。-The 2 division calculation CRC code mode, generating polynomial for CRC-16 allow input characters, there are errors of complete function.
Platform: | Size: 1024 | Author: | Hits:

[Other] CRC-16

Description: 循环冗余校验16位的，c语言编程环境，能够正常运行，程序详细注释-16 bit cyclic redundancy check, C language programming environment, normal operation, procedures detailed notes
Platform: | Size: 228352 | Author: hongzhe | Hits:

[Communication] crc

Description: 自己编写的CRC16校验小程序，自动计算CRC 16值-I have written a small program CRC16 checksum automatically calculated value CRC 16
Platform: | Size: 5120 | Author: 患过风伤 | Hits:
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