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[VHDL-FPGA-Verilog] MAC

Description: 10M/100M以太网mac子层802.3协议的源代码，包括半双工和全双工。-Mac sublayer 10M/100M Ethernet 802.3 protocol source code, including half-duplex and full duplex.
Platform: | Size: 122880 | Author: fiercewind | Hits:

[VHDL-FPGA-Verilog] ldpc_decoder_802_3an

Description: 802.3an ldpc码编码、译码设计，使用VERILOG hdl语言编写，包括测试代码，-802.3an ldpc code encoding, decoding the design, use of language VERILOG hdl, including test code,
Platform: | Size: 788480 | Author: 聂样 | Hits:

[Other] ldpc_decoder_802_3an.tar

Description: 802.3an Ethernet 以太网络 LDPC Verilog 网表实现-802.3an Ethernet Ethernet LDPC Verilog netlist to achieve
Platform: | Size: 914432 | Author: | Hits:

[Program doc] xge_mac_latest.tar

Description: Language - Verilog. The 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defined in IEEE Std 802.3ae. -Language- Verilog. The 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defined in IEEE Std 802.3ae.
Platform: | Size: 813056 | Author: Maxim | Hits:

[VHDL-FPGA-Verilog] ldpc_decoder_802_3an_latest.tar

Description: 802.3an ldpc decoder verilog 源码
Platform: | Size: 884736 | Author: 杨振飞 | Hits:

[VHDL-FPGA-Verilog] ldpc_encoder_802_3an_latest.tar

Description: 适用于10GBase-T的以太网(802.3an协议)LDPC, VERILOG语言编写，可以应用在LATTICEXP2系列芯片上，基于Gallager算法。-LDPC encoder for 10GBase-T Ethernet (802.3an), based on Gallager s A algorithm
Platform: | Size: 620544 | Author: liang | Hits:

[VHDL-FPGA-Verilog] Perl_for_CRC

Description: Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redundancy Check standards are CRC-8, CRC-12, CRC-16, CRC-32, and CRC-CCIT. This application note discusses the implementation of an IEEE 802.3 CRC in a Virtex™ device. The reference design provided with this application note provides Verilog point solutions for CRC-8, CRC-12, CRC-16, and CRC-32. The Perl script (crcgen.pl) used to generate this code is also included. The script generates Verilog source for CRC circuitry of any width (8, 12, 16, 32), any polynomial, and any data input width.-Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redundancy Check standards are CRC-8, CRC-12, CRC-16, CRC-32, and CRC-CCIT. This application note discusses the implementation of an IEEE 802.3 CRC in a Virtex ™ device. The reference design provided with this application note provides Verilog point solutions for CRC-8 , CRC-12, CRC-16, and CRC-32. The Perl script (crcgen.pl) used to generate this code is also included. The script generates Verilog source for CRC circuitry of any width (8, 12, 16, 32 ), any polynomial, and any data input width.
Platform: | Size: 90112 | Author: 尤恺元 | Hits:

[Communication-Mobile] ethmac10_100M

Description: 以太网IP Core 它实现10/100 Mbps的MAC控制器功能。它是在IEEE802.3和802.3u 标准下设计实现的。-The Ethernet IP Core is a 10/100 Media Access Controller (MAC). It consists of a synthesizable Verilog RTL core that provides all features necessary to implement the Layer 2 protocol of the Ethernet standard. It is designed to run according to the IEEE 802.3 and 802.3u specifications that define the 10 Mbps and 100 Mbps Ethernet standards, respectively.
Platform: | Size: 18925568 | Author: haizi | Hits:

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