Description: 使用68013的测试程序，包含68013固件程序（采用slave FIFO bulk同步读写，EP2 OUT，EP6 IN），驱动，PC端测试用程序。CPLD的VHDL代码-Test procedures for the use of 68,013, including 68,013 firmware (using the synchronous slave FIFO bulk read and write, EP2 OUT, EP6 IN), driver, PC-side test procedures. VHDL code of CPLD Platform: |
Size: 4731904 |
Author:李华 |
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Description: 介绍了此控制器与FPGA接口的控制和HDL (硬件描述语言)实现方法。利用CY7C68013控制器的
Slave F IFO从机方式,用Verilog HDL在FPGA中产生相应的控制信号,实现对数据的快速读写。试验
结果表明此方案传输速度快、数据准确,可扩展到其他需要通过USB进行快速数据传输的系统中-This paper describes the controller and the FPGA interface to control and HDL (hardware description language) implementations. Use CY7C68013 controller Slave F IFO slave mode, using Verilog HDL in the FPGA generate a corresponding control signal to achieve fast read and write data. The results show that this program transmission speed, accurate data can be expanded to other needs through the USB for fast data transfer system Platform: |
Size: 365568 |
Author:余岳衡 |
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