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[Other resource] the-design-of-16-bit-cpu DL : 0: 用vhdl硬件语言设计的16位cpu，上传的压缩包既包含源代码又包含详细的文档说明。-with vhdl hardware design language of the 16 cpu, Upload compressed contains both the source code also contains a detailed document shows.
Date : 2008-10-13 Size : 125.11kb User : 晶晶
[VHDL-FPGA-Verilog] the-design-of-16-bit-cpu DL : 0: 用vhdl硬件语言设计的16位cpu，上传的压缩包既包含源代码又包含详细的文档说明。-with vhdl hardware design language of the 16 cpu, Upload compressed contains both the source code also contains a detailed document shows.
Date : 2025-07-13 Size : 125kb User : 晶晶
[VHDL-FPGA-Verilog] CPU DL : 0: 简单的16位CPU的VHDL设计 vhdl代码和cpu设计过程-Simple 16-bit CPU design of the VHDL code and VHDL design process cpu
Date : 2025-07-13 Size : 1.42mb User : kilva
[VHDL-FPGA-Verilog] MyCPU16 DL : 0: 16位cpu设计VHDL源码，其中包括alu，clock，memory等部分的设计-16 cpu design VHDL source code, including alu, clock, memory and other parts of the design
Date : 2025-07-13 Size : 1.04mb User : 孙冰
[VHDL-FPGA-Verilog] 8-cpu DL : 0: 8位CPU的VHDL设计,16条指令系统,以及部分测试代码,开发工具是quartusii_60_pc-8-bit CPU of the VHDL design, 16 instruction, as well as some of the test code, development tools is quartusii_60_pc
Date : 2025-07-13 Size : 3kb User : FJ
[OS program] 16cpu DL : 0: 实现16位的cpu设计内容使用verilog hdl实现，具体的实现步骤方法，都已经写到文档里面去了！-To achieve 16-bit design of the contents of the cpu using verilog hdl achieve, the specific methods to achieve these steps have already been written inside the document went to!
Date : 2025-07-13 Size : 430kb User : gimel_sh
[ARM-PowerPC-ColdFire-MIPS] pipeline DL : 0: 用Quartus II 设计的3级流水CPU，指令采用二次重叠执行方式-Quartus II design with three-stage pipeline CPU, instruction execution overlaps with the second time
Date : 2025-07-13 Size : 2.89mb User : kevin
[VHDL-FPGA-Verilog] CPU DL : 0: 用VHDL编的简易16位和8位CPU，可完成加减乘法移位等功能，拥有源码和设计文档，资料齐全-Compiled with VHDL simple 16-bit and 8-bit CPU, to be completed by addition and subtraction multiplication shift functions, with source code and design documents, data and complete
Date : 2025-07-13 Size : 1.42mb User : 雄鹰
[ARM-PowerPC-ColdFire-MIPS] 16-bit_cpu_design DL : 0: 详细介绍了如何设计一个简单的16位cpu.其中包含了从最基础的指令系统开始到最复杂的cu控制器的设计思路，方案.最后还介绍了一些有关vhdl语言的用法,并给出了具体的cpu部件的vhdl代码,从而帮助大家更为深刻的学习如何设计一个简单的cpu-Described in detail how to design a simple 16-bit cpu. Which contains the most basic instruction from the beginning to the most complex cu controller design ideas, program. Finally the author describes some of the vhdl language usage, and gives vhdl cpu specific parts of the code to help you more deeply to learn how to design a simple cpu
Date : 2025-07-13 Size : 1mb User : 罗高
[VHDL-FPGA-Verilog] cpu DL : 0: 16位的CPU的VHDL程序~~还有附加的生成波形，可以应用于课程设计中-16-bit CPU, VHDL ~ ~ There are additional procedures for generating waveforms, can be applied to curriculum design
Date : 2025-07-13 Size : 1mb User : liuying
[VHDL-FPGA-Verilog] cpu16 DL : 0: 16位cpu设计vhdl源码。主要实现risc机器模型-16-bit cpu design code
Date : 2025-07-13 Size : 178kb User : peterloo
[VHDL-FPGA-Verilog] cpu DL : 0: 给定指令系统的处理器设计,指令字长16位，包含10种操作-Given instruction processor design, 16-bit instruction word length, contains 10 kinds of operations
Date : 2025-07-13 Size : 1.04mb User : 姜健
[VHDL-FPGA-Verilog] zxcpu DL : 0: 用VHDL语言设计了一个含10条指令的RISC处理器。假定主存可以在一个始终周期内完成依次读写操作且和CPU同步，系统使用一个主存单元。处理器指令字长16位，包含8个通用寄存器，1个16位的指令寄存器和一个16位的程序记数器。处理器的地址总线宽度16位。数据总线宽度16位，取指和数据访问均在一跳蝻数据总线。处理器支持包含LDA，STA，MOV，MVI，ADD，SUB，AND，OR，JZ，JMP十条指令。其中仅有LDA和STA是访存指令。-VHDL language design with a RISC processor with 10 instruction. Assume that main memory can be completed in one cycle is always followed and the CPU read and write operations and the synchronization system uses a main memory unit. 16-bit instruction word processor, including 8 general purpose registers, a 16-bit instruction register and a 16-bit program counter. Processor' s address bus width 16 bits. 16-bit data bus width, fetch and data access are in the hop hoppers data bus. Processor support includes LDA, STA, MOV, MVI, ADD, SUB, AND, OR, JZ, JMP ten instructions. LDA and STA is the only one memory access instructions.
Date : 2025-07-13 Size : 1.03mb User : zhaoshu
[VHDL-FPGA-Verilog] vhdl_16CPU DL : 0: 16位CPU设计，采用VHDL语言，自带测试汇编语言，能实现基本运算和移位、跳转等操作-16-bit CPU design, using VHDL language, self-test assembly language, to achieve the basic operations and shift operations such as jump
Date : 2025-07-13 Size : 962kb User : 戈多
[VHDL-FPGA-Verilog] CPU-with-VHDL-16-32 DL : 0: 在quartus中运行的32位指令集的16位CPU程序，模块化设计，包括MBR, BR, MR, ACC, MAR, PC, IR, CU, ROM, RAM, ALU等模块-In the the quartus run 32 16-bit CPU instruction set procedures, modular design, including the MBR, BR, MR, the ACC, the MAR, the PC, the IR CU, the ROM, RAM, ALU and other modules
Date : 2025-07-13 Size : 1.58mb User :
[Other] 16-bit-CPU DL : 0: 单周期16位CPU的设计,我们的计算机组成原理课设，可以实现R型、I型和J型指令，内有报告和指导书-Single-cycle 16-bit CPU design, our Principles of Computer Organization class set, you can achieve R-type, type I, and J-type instructions, reports and instructions
Date : 2025-07-13 Size : 3.99mb User : 大空翼
[VHDL-FPGA-Verilog] cpu DL : 0: 计算机设计与实践实验 16位cpu设计使用用VHDL语言 -16-bit cpu design with VHDL
Date : 2025-07-13 Size : 1002kb User : yuwentao
[source in ebook] 16-CISC-CPU-design DL : 0: 16位精简指令集的CPU设计，有完整的步骤和原程序可供学习-16-bit RISC CPU design, complete steps and the original program for learning
Date : 2025-07-13 Size : 683kb User : 何宗苗
[Windows Develop] CPU DL : 0: 基于Basys3的16位CPU设计，含有指令集，可以控制Basys3的LED灯，并且通过板子上的开关，调节流水灯的模式(16 bit CPU design based on Basys3, containing instruction set, can control the Basys3 LED lights, and through the switch on the board, adjust the water lamp mode)
Date : 2025-07-13 Size : 7kb User : 当当当当1
[VHDL-FPGA-Verilog] cpu_2013 DL : 0: 简化的16位的cpu的设计，有缓冲器，指令存储器，数据存储器等基本模块组成(The simplified 16 bit CPU design consists of a buffer, instruction memory, data memory and other basic modules)
Date : 2025-07-13 Size : 17.42mb User : 施魍魉

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