To achieve 16-bit design of the contents of the cpu using verilog hdl achieve, the specific methods to achieve these steps have already been written inside the document went to!

16位cpu设计
...........\CPU.v
...........\decoder.v
...........\ram.v
...........\RISC_CPU设计练习.doc
...........\rom.v
...........\test.v
...........\test1.dat
...........\test1.pro
...........\test2.dat
...........\test2.pro
...........\test3.dat
...........\test3.pro
...........\test4.dat
...........\test4.pro
...........\test5.dat
...........\test5.PRO
...........\vsim.wlf
...........\模拟结果.txt
...........\说明.txt

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