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[File Format] WinDLXcourseDesign DL : 0: WinDLX的实验,除了代码优化的部分全部完成,包括流水线的分析.-WinDLX experiments, in addition to the optimization of code completion, including pipeline analysis.
Date : 2025-12-20 Size : 66kb User : 罗本
[File Format] xieyingqi DL : 0: 信息管路系统!有源代码!论文!开题报告!-Information pipeline system! Active code! Papers! Open title report!
Date : 2025-12-20 Size : 1.76mb User : 张斌斌
[File Format] Temperature-Sensor DL : 0: 　DS18B20数字温度传感器接线方便，封装成后可应用于多种场合，如管道-DS18B20 digital temperature sensor wiring easy, can be used in a variety of packages to the occasions, such as pipeline
Date : 2025-12-20 Size : 67kb User : 单晴
[File Format] design_and_implementation_of_a_cfar_processor_for DL : 0: Real-time performance of adaptive digital signal processing algorithms is required in many applications but it often means a high computational load for many conventional processors. In this paper, we present a configurable hardware architecture for adaptive processing of noisy signals for target detection based on Constant False Alarm Rate (CFAR) algorithms. The architecture has been designed to deal with parallel/pipeline processing and to be configured for three versions of CFAR algorithms, the Cell-Average, the Max and the Min CFAR. The architecture has been implemented on a Field Programmable Gate Array (FPGA) with a good performance improvement over software implementations. Results are presented and discussed.
Date : 2025-12-20 Size : 57kb User : nacer1606
[File Format] Oil-Pipeline-Project DL : 0: Oil Piepline full Excel Design
Date : 2025-12-20 Size : 690kb User : Chukwuemeka
[File Format] Water-Pipeline-Project-P-Comparison DL : 0: Water Pipeline Full Excel Design with Comparison with Oil
Date : 2025-12-20 Size : 714kb User : Chukwuemeka
[File Format] Pipeline-running DL : 0: 本文主要对云南大红山管道的运行状况进行了详细的描述，介绍了其中各部分主要的部件。-This paper focuses on the health of Yunnan Dahongshan pipes were described in detail, which describes the main components of each part.
Date : 2025-12-20 Size : 2.46mb User : 牟竹青
[File Format] fp_adder_subtractor DL : 0: 本文介绍用于计算IEEE 754标准的双精度64位浮点二进制数加/减法硬件架构。-In this article, an optimized pipeline hardware architecture for computing IEEE 754 standard double precision 64-bit floating point binary number addition/subtraction was proposed.
Date : 2025-12-20 Size : 695kb User : Jenny