Search - FIFO in vhdl

Search - FIFO in vhdl - List

[Software Engineering] Asyn_FIFO_Design DL : 0: 异步FIFO设计的说明文档，需要注意的问题以及源码（在文中有）。是标准的异步FIFO，可综合。-Asynchronous FIFO design documentation, as well as the need to pay attention to source code (in the text have). Is a standard asynchronous FIFO, can be integrated.
Date : 2025-12-19 Size : 223kb User : 刘强
[Software Engineering] multiplier_8bit DL : 0: 异步FIFO设计的说明文档，需要注意的问题以及源码（在文中有）。是标准的异步FIFO，可综合。-Asynchronous FIFO design documentation, as well as the need to pay attention to source code (in the text have). Is a standard asynchronous FIFO, can be integrated.
Date : 2025-12-19 Size : 45kb User : 刘强
[Software Engineering] spartan6_fpga_blockram_user_guide DL : 0: Spartan6　FPGA中的块存储器使用指南，可以构建为FIFO，ROM，RAM，移位寄存器等。-Spartan6 FPGA block memory in the User Guide, you can build for FIFO, ROM, RAM, shift registers and so on.
Date : 2025-12-19 Size : 368kb User : james
[Software Engineering] ThedesignofUniversalAsynchronousReceiverTransmitte DL : 0: 本课题所设计的UART支持标准的RS．232C传输协议，主要设计有发送模块、接收模块、线路控制与中断仲裁模块、Modem控制模块以及两个独立的数据缓冲区FIFO模块。该模块具有可变的波特率、数据帧长度以及奇偶校验方式，还有多种中断源、中断优先级、较强的抗干扰数据接收能力以及芯片内部自诊断的能力，模块内分开的接收和发送数据缓冲寄存器能实现全双工通信。除此之外最重要的是利用口模块复用技术设计数据缓冲区FIFO，采用两种可选择的数据缓冲模式。这样既可以应用于高速的数据传输环境，也能适合低速的数据传输场合，因此可以达到资源利用的最大化。-According to the characteristics of the UART and the portability advantage of FPGA designs，this paper puts forward an embedded UART design method based on FPGA chips．The design method includes description form of FSM and design approach of Top-Down．It’S good to take advantage of VHDL to program the slave module and top module of UART，and then integrate them into the interior of FPGA chip．In this case it improves not only the disadvantage of the traditional UART chips but also makes the whole system more compact and more reliable．
Date : 2025-12-19 Size : 4.84mb User : mabeibei