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VHDL实例,在MAX+Plus+II下开发-VHDL example, the MAX II Plus under development
Date : 2008-10-13 Size : 1.22mb User : 孙庆波

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VHDL实例,在MAX+Plus+II下开发-VHDL example, the MAX II Plus under development
Date : 2025-12-28 Size : 1.22mb User : 孙庆波

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提出了正交频分复用(O FDM ) 系统中一种新的载波频偏估计算法L 载波频偏估计过程可分 为获取和跟踪, 其中, 获取过程和时间同步是同时完成的L新算法可实现的最大载波频偏获取范围 是整个信号带宽的一半L新的跟踪算法是一个最大似然算法, 在加性白噪声高斯信道(AW GN ) 下, 当N (训练序列长度的一半) 等于128 时, 其性能比Schm idl 算法提高约7127 dB 在多经信道下, 当 信噪比不是很高时, 新算法仍具有优势L-new carrier f requency offset est imat ion scheme in o rthogonal f requency division mu lt ip lex ing (O FDM ) system is p ropo sed. The carrier f requency offset est i2 mat ion includes acqu isit ion and t rack ing, and acqu isit ion as w ell as t im ing synch ro2 n izat ion can be perfo rmed simu ltaneou sly w ith h igh accu racy. The max imum acqu i2 sit ion range can be up to one half of overall signal bandw idth. The p ropo sed t rack2 ing est imato r is a max imum 2likelihood est imato r, and in AW GN channel, abou t 7127dB imp rovemen t is ob tained compared to the Schm idl’s algo rithm w hen N = 128 in mu lt ipath channel, the p ropo sed algo rithm wo rk s w ell at moderate SNR.
Date : 2025-12-28 Size : 183kb User : 卫海宁

福州大学07级eda实验报告。。。一共八九份 包含实验指导书 实验一 利用原理图输入法设计4位全加器 一、实验目的: 掌握利用原理图输入法设计简单组合电路的方法,掌握MAX+plusII的层次化设计方法。通过一个4位全加器的设计,熟悉用EDA软件进行电路设计的详细流程。 -07 eda, Fuzhou University lab reports. . . A total of 89 experimental instructions were included experiments using schematic entry method for a 4-bit full adder design one experiment: master the use of schematic design of a simple combination of input circuit means, to grasp MAX+ plusII the hierarchical design method. By a 4-bit full adder design, familiar with the circuit design using EDA software, a detailed process.
Date : 2025-12-28 Size : 846kb User : 林明明

可以算出指数每个时点的最大回撤率,并作图。(The code can help you calculate max drawdown rate for each date, and draw a figure.)
Date : 2025-12-28 Size : 15kb User : EdgarK
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