Search - v c - CodeBus

Search - v c - List

[VHDL-FPGA-Verilog] crc16_ccitt DL : 0: crc_table.c is for reset seed( 0000 ) crc_table_1.c is for reset seed( ffff) CRC16_D8_m.v is a verilog module of byte paralle crc. CRC16_D8_m_tb.v is the testbench file of above module. -crc_table.c is for reset seed (0000) crc_table_1.c is for reset seed (ffff) CRC16_D8_m.v is a verilog module of byte paralle crc.CRC16_D8_m_tb.v is the testbench file of above module.
Date : 2025-12-30 Size : 3kb User : 樊文杰
[VHDL-FPGA-Verilog] sourcefile DL : 0: 在Altera公司的Cyclone系列FPGA开发板上试验的按键中断程序，希望对那些学习中断开发的初学者有帮助。 pio_key.v是verilog编写的按键中断程序，对应四个按键，按其中任何一个键都可以发送一个中断； keyint.c是Nios中编写的C程序，用于检测按键的中断，如果检测到中断，会检测是哪个按键按下，从而执行相应的程序！ -In Altera' s Cyclone series FPGA development board interrupt key test procedures, interruption of hope to those who study the development of help for beginners. verilog prepared pio_key.v button is interrupted procedures, corresponding to the four keys, in accordance with any one key can send an interrupt keyint.c is prepared Nios of C procedures for detecting the interruption of keys, if the interruption is detected, will detect which button is depressed, thus the implementation of appropriate procedures!
Date : 2025-12-30 Size : 3kb User : 王陶
[VHDL-FPGA-Verilog] DE2_NIOS_HOST_MOUSE_VGA DL : 0: 在DE2开发板上实现的VGA输出游戏。硬件用Verilog语言编写，在Quartus上编译；软件用C语言编写，在Nios2上编译运行。把DE2板和显示器键盘连起来即可使用。-Development in the DE2 board game to achieve the VGA output. Hardware using Verilog language, compiled in the Quartus software with C language, compiled to run in Nios2. The DE2 board and display can be used to connect the keyboard.
Date : 2025-12-30 Size : 1.55mb User : 符玉襄
[VHDL-FPGA-Verilog] shiboqi DL : 0: 此为数字存储双宗示波器内还有C和V程序非常完整-This is a digital storage oscilloscope were within two-C and V are very complete program
Date : 2025-12-30 Size : 830kb User : 叶问
[VHDL-FPGA-Verilog] verilog_testbench_genetator DL : 0: 这是一个perl程序只需要在cmd中运行，参数为你的Verilog名字功能是:半自动生成Verilog的testbench，提高编码效率-#-----READ ME of verilog_tb_generate.pl----------------------| # | #-----copyright(C) Xzmeng 2010-------------------------------| # | #Date:2010-12-18 21:55:48------------------------------------| # | #Run the pl followed with the verlog file name,such as aaa.v | #Put the original verilog file(.v) in the current directory. | #------------------------------------------------------------| # | #And you need to gurrantee that there is only one "input" or | #"output" per line. | # | #------------------------------------------------------------|
Date : 2025-12-30 Size : 2kb User : zishan
[VHDL-FPGA-Verilog] Micron_SDRAM_CNTR DL : 0: /****************************************************************************** * * File Name: sdrm.v * Version: 1.14 * Date: Sept 9, 1999 * Description: Top level module * Dependencies: sdrm_t, sys_int * * Company: Xilinx * * * Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY * WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR * A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. * * Copyright (c) 1998 Xilinx, Inc. * All rights reserved * ******************************************************************************/-/****************************************************************************** * * File Name: sdrm.v * Version: 1.14 * Date: Sept 9, 1999 * Description: Top level module * Dependencies: sdrm_t, sys_int * * Company: Xilinx * * * Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY * WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR * A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. * * Copyright (c) 1998 Xilinx, Inc. * All rights reserved * ******************************************************************************/
Date : 2025-12-30 Size : 291kb User : shangdawei
[VHDL-FPGA-Verilog] AssignmentP4 DL : 0: Assignment 4: 1. Analyze and simulate the following code lists (code1 and code 2) with the same input signals shown below by presenting POW and OL. If the data type of “a, b, c, d, u, v, w, x, y, z” is declared as std_logic, what will the simulation outputs be changed?
Date : 2025-12-30 Size : 168kb User : 魏攸
[VHDL-FPGA-Verilog] có t?ng chi?u dài to?n b? cay v?i DL : 0: invalid description, it should be english
Date : 2025-12-30 Size : 499kb User : Danh