/****************************************************************************** * * File Name: sdrm.v * Version: 1.14 * Date: Sept 9, 1999 * Description: Top level module * Dependencies: sdrm_t, sys_int * * Company: Xilinx * * * Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY * WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR * A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. * * Copyright (c) 1998 Xilinx, Inc. * All rights reserved * ******************************************************************************/

verilog\README
.......\synth\run_synth
.......\.....\sdrm.edf
.......\.....\sdrm.scr
.......\.....\setup.scr
.......\.rc\brst_cntr.v
.......\...\cslt_cntr.v
.......\...\define.v
.......\...\ki_cntr.v
.......\...\rcd_cntr.v
.......\...\ref_cntr.v
.......\...\sdrm.v
.......\...\sdrmc_state.v
.......\...\sdrm_t.v
.......\...\sys_int.v
.......\post_route\post_route.cfg
.......\..........\post_route.log
.......\..........\post_route.vpd
.......\..........\run_sim
.......\..........\sdrm_par.sdf
.......\..........\sdrm_par.v
.......\..........\string_decode_post_route.v
.......\..........\tb_post_route.v
.......\.ar\run_par
.......\...\sdrm.edf
.......\...\sdrm.ucf
.......\...\sdrm_par.sdf
.......\...\sdrm_par.v
.......\micron\bank0.txt
.......\......\bank1.txt
.......\......\mt48lc1m16a1-8a.v
.......\......\mt48lc1m16a1.v
.......\......\test.v
.......\func_sim\func_sim.cfg
.......\........\func_sim.log
.......\........\func_sim.vpd
.......\........\run_sim
.......\........\string_decode_fn.v
.......\........\tb_sdrm.v
.......\synth
.......\src
.......\post_route
.......\par
.......\micron
.......\func_sim
verilog

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