Search - traffic signal control

Search - traffic signal control - List

[VHDL-FPGA-Verilog] codeofvhdl2006 DL : 1: 【经典设计】VHDL源代码下载～～其中经典的设计有：【自动售货机】、【电子钟】、【红绿灯交通信号系统】、【步进电机定位控制系统】、【直流电机速度控制系统】、【计算器】、【点阵列LED显示控制系统】基本数字逻辑设计有：【锁存器】、【多路选择器】、【三态门】、【双向输入|输出端口】、【内部（缓冲）信号】、【编码转换】、【加法器】、【编码器/译码器】、【4位乘法器】、【只读存储器】、【RSFF触发器】、【DFF触发器】、【JKFF触发器】、【计数器】、【分频器】、【寄存器】、【状态机】 - [ Classics design ] the VHDL source code downloads ~ ~ classics the design to include: [ Vending machine ], [ electron clock ], [ traffic light traffic signal system ], [ step of 杩涚數 machine localization control system ], [ direct current machine speed control system ], [ calculator ], [ array LED display control system ] the basic numeral logical design includes: [ Latch ], [ multichannel selector ], [ 涓夋
Date : 2025-12-16 Size : 43kb User : senkong
[VHDL-FPGA-Verilog] trafficlightvhdlcode DL : 0: VHDL实现的交通灯程序，可以定时南北和东西方向的交通灯信号，控制红黄绿各灯亮的时间，并考虑紧急情况如有救护车通过-VHDL procedures realize the traffic lights, you can regularly north-south and east-west direction of the traffic lights signal control red, yellow, and green lights all the time, and to consider the adoption of an emergency if the ambulance
Date : 2025-12-16 Size : 568kb User : dongming
[VHDL-FPGA-Verilog] traffic_light DL : 0: 基于FPGA的交通灯系统控制程序。用的是verilog.-FPGA-based traffic signal system control procedures. Using verilog.
Date : 2025-12-16 Size : 141kb User : fuyu
[VHDL-FPGA-Verilog] Traffic_Light DL : 0: 在XILINX环境下，实现交通信号灯控制，VHDL语言编写。-In the XILINX environment, the achievement of traffic signal control, VHDL language.
Date : 2025-12-16 Size : 534kb User : heh
[VHDL-FPGA-Verilog] jtd DL : 0: 交通灯控制程序.实现十字路口的交通灯控制.使用vhdl编写,使用方便.-Traffic lights control procedures. The realization of the traffic signal controlled crossroads. The use of VHDL to prepare and easy to use.
Date : 2025-12-16 Size : 701kb User : good
[VHDL-FPGA-Verilog] TheLEDlightsbasedonVHDLprogram DL : 0: 基于VHDL实现LED等的控制，可作为后续交通灯设计的基础程序。已调试运行成功。-LED-based VHDL to achieve such control, can be used as the basis for follow-up procedures for traffic signal design. Has been successful commissioning.
Date : 2025-12-16 Size : 292kb User : 戚澈
[VHDL-FPGA-Verilog] traffic DL : 0: 采用VHDL语言编写的控制交通灯工作的程序。分为四个部分：1，分频器，2，计数并产生控制信号，3，交通灯信号产生，4，交通灯总体描述。点击lzh6.aws打开工作空间-VHDL language used to control traffic lights work procedures. Divided into four parts: 1, divider, 2, count and generates control signals, 3, traffic signal generation, 4, a general description of traffic lights
Date : 2025-12-16 Size : 20kb User : 李修函
[VHDL-FPGA-Verilog] EDA5 DL : 0: 交通灯控制器设计：1．有MR(主红)、MY（主黄）、MG（主绿）、CR（乡红）、CY（乡黄）、CG（乡绿）六盏交通灯需要控制； 2．交通灯由绿→红有4秒黄灯亮的间隔时间，由红→绿没有间隔时间； 3．系统有MRCY、MRCG、MYCR、MGCR四个状态； 4．相间公路右侧各埋有一个传感器，当有车辆通过相间公路时，发出请求信号S； 5．平时系统停留在MGCR状态，一旦S信号有效，经MRCY转入MRCG状态，但要保证MRCG状态也不得短于一分钟； 6．一旦S信号无效，系统脱离MRCG状态。随即经MRCY转入进入MGCR状态，计时S信号一直有效，MRCG状态也不得长于20秒钟。 -Traffic light controller design: 1. With MR (the main red), MY (Master Wong), MG (Master Green), CR (township red), CY (Rural yellow), CG (village green) six traffic lights need to control 2. → red traffic light from green to bright yellow with 4 seconds intervals, not from red → green interval 3. System MRCY, MRCG, MYCR, MGCR four states 4. The right side of the road white buried a sensor, when a vehicle through the white road, the request signal S 5. MGCR usually stay in the state system, once the S signal is valid, the MRCY into MRCG state, but also to ensure that the state shall not be less MRCG one minute 6. Once the S signal is invalid, the system from MRCG state. Then transferred into MGCR by MRCY state S signal timing has been effective, MRCG status is no longer than 20 seconds.
Date : 2025-12-16 Size : 1013kb User : 周旋
[VHDL-FPGA-Verilog] traffic-control DL : 0: 设计一个只有四种信号灯的交通灯控制器：由一条主干道和—条支干道汇合成十字路口，在每个入口处设置红、绿、黄、左拐允许四盏信号灯，红灯亮禁止通行，绿灯亮允许通行，黄灯亮则给行驶中的车辆有时间停在禁行线外，左拐灯亮允许车辆向左拐弯。信号灯变换次序为：主支干道交替允许通行，主干道每次放行40s，亮5s红灯让行驶中的车辆有时间停到禁行线外，左拐放行15s，克5s红灯；支干道放行30s，亮5s黄灯，左拐放行15s，亮5s红灯……。各计时电路为倒计时显示。-Only four traffic lights to design a traffic signal controller: from a main road and- bar branch roads merged into the crossroads, the entrance of each set of red, green, yellow, turn left to allow four lights, red light is closed to traffic, the green light to allow passage, the yellow light is to have time to moving vehicles parked outside the line of the cut line, allowing the vehicle to the left turn left turn lights. The order of signal conversion: the main branch roads alternately allow passage, each trunk release 40s, 5s bright red light to moving vehicles have time to stop the entry lane, the left release of 15s, 5s grams of red light branch trunk release 30s, 5s bright yellow light, turn left release 15s, 5s red light ... .... The countdown timer circuit.
Date : 2025-12-16 Size : 15kb User : 小石头
[VHDL-FPGA-Verilog] t33 DL : 0: 交通灯控制系统某路口有一条主干道和一条支干路交叉而成。根据统计，主干道的交通流量为支路的两倍。要求： 1)、正常情况下，两路轮流放行，且主干道的放流时间是支路的两倍。信号转换时，按照以下规律显示：从通行变为停止时，按绿→黄→红次序变化；从停止变为通行时，按红→闪动→绿次序变化；主干道与支路的显示必须保证它们是交叉进行的。 2)、当路上出现特种车辆(如警车、消防车等)时，该路口应将它立即放行，并使另一方向停止。如果两个方向同时出现特种车，应时主干道的车辆先放行。-Traffic light control system A main road and a junction with a cross made of branches trunks. According to Commission Meter, main road traffic to slip twice. Requirements: 1), under normal circumstances, release of two turns, and the main road of releasing time Is the branch twice. Signal conversion, the following rule shows: From the passage into a stop, press the green → yellow → red sequence changes Into a passage from the stop, press the flashing red → green → order changes Trunk and branch display must ensure that they are interleaved. 2), when on the road there special vehicles (such as police cars, fire engines, etc.), the Road Mouth it should be released immediately, and to stop the other direction. If the two directions At the same time there special vehicles, seasonal vehicles first release trunk
Date : 2025-12-16 Size : 2kb User : 胡芳洲
[VHDL-FPGA-Verilog] traffic DL : 0: CLK：为同步时钟； EN：使能信号，为1的话，则控制器开始工作； LAMPA：控制A方向四盏灯的亮灭；其中，LAMPA0~LAMPA3 ，分别控制A方向的-CLK: synchronized clock EN: Enable signal is 1, then the controller starts to work LAMPA: control the direction A four lamp light off which, LAMPA0, ~ LAMPA3, respectively, to control the direction of A
Date : 2025-12-16 Size : 314kb User : happy
[VHDL-FPGA-Verilog] Intersection-traffic-lights-control DL : 0: 基于FPGA的十字路口智能交通信号灯控制系统的VHDL程序代码-FPGA the crossroads of intelligent traffic signal control systems-based process and VHDL code
Date : 2025-12-16 Size : 1kb User : fandi
[VHDL-FPGA-Verilog] trafficlight DL : 0: 基于VHDL的十字路口交通灯控制系统设计与实现,定时器模块由25S、5S、20S三个定时器组成，分别确定相应信号灯亮的时间。三个定时器采用以秒脉冲为时钟的计数器实现。eg、ey、er分别是三个定时器的工作使能信号，tm25、tm5、tm20是三个定时器的计数结束指示信号。控制模块是对系统工作状态的转换进行控制，根据交通规则可得系统状态转换情况。ar、ay、ag br、by、bg分别表示由控制器输出的A道和B道的红、黄、绿信号灯亮的时间；eg、ey、er分别表示由控制器输出的控制25S、5S、20S三个定时器的工作使能信号。-Based on VHDL crossroads traffic lights control system design and implementation, the timer module from 25S, 5S, 20S, three timer composition, respectively, to determine the corresponding signal light time. Three timer a second pulse of the clock counter. eg, ey, er, respectively, three timer enable signal tm25, tm5, of tm20 the end of the three timers count indication signal. The control module to control the conversion of the system working state conversions in accordance with the rules of the road can get system status. ar, ay, ag br, by, bg, respectively output by the controller of A and B Road, red, yellow, green signal light eg, ey, er, respectively, by the control of the controller output 25S, 5S, 20S, three timer enable signal.
Date : 2025-12-16 Size : 181kb User : 蔡利波
[VHDL-FPGA-Verilog] Traffic-lights-program DL : 0: 设计一个交通信号灯控制电路。要求： 1、主干道和支干道交替放行，主干道每次放行30秒，支干道每次放行20秒。 2、每次绿灯变红灯时，黄灯先亮5秒钟，此时原红灯不变。 3、用十进制数字（递增计数）显示放行和等待时间。-The design of a traffic signal control circuits. Requirements: 1, main roads and branch roads alternately release, the main road each release of 30 seconds, the branch roads each release of 20 seconds. 2, each time the green light change when the red light, yellow light on for 5 seconds, then the original red light unchanged. Three decimal digits (counting) shows the release and waiting time.
Date : 2025-12-16 Size : 19kb User : 胡伟红
[VHDL-FPGA-Verilog] VHDL_JTD DL : 0: 设计任务要求控制器部分的状态转移图和流程图；交通灯控制器：用于十字路口的交通灯控制器。实验要求：（1）东西方向各有一组红,黄,绿灯用于指挥交通，红，黄，绿的持续时间分别为25s,5s,20s 。（2）当有紧急情况（如消防车）时，两个方向均为红灯亮，计时停止，当特殊情况结束后，控制器恢复原来状态，正常工作。（3）两组数码管，以倒计时方式显示两个方向允许通行或禁止通行的时间。-Part of the design task requires the controller state transition diagrams and flow charts traffic signal controller: the controller for the traffic light intersection. Experimental requirements: (1) east-west direction have a group of red, yellow, green light for directing traffic, red, yellow and green are the duration of 25s, 5s, 20s. (2) When there is an emergency situation (such as fire engines), the two directions are the red light, time stops, when the end of special circumstances, the controller to restore the original state of work. (3) two sets of digital control to display the countdown in both directions to allow access or prohibit the passage of time.
Date : 2025-12-16 Size : 143kb User : zzx
[VHDL-FPGA-Verilog] Traffic_Light DL : 0: FPGA模拟实现的交通灯控制系统，语言为Verilog，环境为QurtursII，默认情况下按预先设定的时间进行倒计时，支持人工控制模式让某一方向信号灯常亮。信号灯采用LED代替-The FPGA simulation realization of traffic light control system, language, Verilog, environment QurtursII, default preset time countdown, support manual control mode for a direction signal lamps lit. Signal lights using LED instead
Date : 2025-12-16 Size : 610kb User : wicoboy
[VHDL-FPGA-Verilog] traffic DL : 0: 交叉口多相位信号控制机，包含分频模块及主控模块，各方向绿灯时间不同，12个led灯分别控制-Multi Phase signal controller with frequency module and main control module, the green light in each direction at different times, 12 led lights control
Date : 2025-12-16 Size : 81kb User : 李祥云
[VHDL-FPGA-Verilog] jiaotongdeng DL : 0: 交通信号灯自动控制器,能下载到FPGA开发板，自动交通灯控制程序，由VHDL编写，环境为QUTUS2-Traffic signal controller, can be downloaded to the FPGA development board, automatic traffic light control procedures, written by VHDL environment QUTUS2
Date : 2025-12-16 Size : 1.72mb User : dengnana
[VHDL-FPGA-Verilog] traffic_control DL : 0: 使用verilog语言编写的双向交通信号控制灯程序，通过状态机转换实现车行道和人行道功能，以cyclone IV系列开发板做为应用平台。-Verilog language using two-way traffic signal control lights procedures, driveway and sidewalk functions via a state machine transition to cyclone IV Series development board as the application platform.
Date : 2025-12-16 Size : 3.49mb User : 郑俊哲
[VHDL-FPGA-Verilog] traffic-light DL : 0: （1） Divid 模块：1Hz 分频模块，开发板提供50MHz 的系统时钟，而该设计交通灯转换以秒为计时单位，对50MHz 分频得到1Hz 脉冲信号。（2） Divid_200 模块: 200Hz 分频模块,用于产生动态扫描模块的时钟。一个数码管稳定显示要求的切换频率要大于50Hz，那么4 个数码管则需要50×4＝200Hz 以上的切换频率才能看到不闪烁并且持续稳定显示的字符，因而扫描频率设定为 200Hz。（3） Control 模块：A、B 方向红绿灯控制模块，红灯、绿灯为20 秒，黄灯为5 秒。并实现计时数据转换，即将数据分为十位显示数据，与各位显示数据，用于数码管显示。（4） saomiao 扫描模块：轮流选通2 位数码管，实现动态扫描，以显示倒计时数据。-(1) Divid module: 1Hz divider module, the development board provides 50MHz system clock, and the design of traffic lights Conversion in seconds for the time unit, the 50MHz frequency to be 1Hz pulse signal. (2) Divid_200 module: 200Hz frequency division module, used to generate the dynamic scanning module clock. A digital tube Stable display requirements of the switching frequency is greater than 50Hz, then the four digital tubes need 50 × 4 200Hz or more Of the switching frequency to see the non-flickering and continuous display of the characters, so the scanning frequency is set to 200Hz. (3) Control module: A, B direction traffic light control module, red, green for 20 seconds, yellow for 5 seconds. And to achieve timing data conversion, the data is divided into ten display data, and you display data for digital display. (4) saomiao scanning module: 2-bit strobe digital control, dynamic scanning to show the countdown data.
Date : 2025-12-16 Size : 521kb User : panda

« 12 »