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Category : VHDL-FPGA-Verilog
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- Update : 2012-11-26
- Size : 181kb
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- Author :蔡****
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Based on VHDL crossroads traffic lights control system design and implementation, the timer module from 25S, 5S, 20S, three timer composition, respectively, to determine the corresponding signal light time. Three timer a second pulse of the clock counter. eg, ey, er, respectively, three timer enable signal tm25, tm5, of tm20 the end of the three timers count indication signal.
The control module to control the conversion of the system working state conversions in accordance with the rules of the road can get system status. ar, ay, ag br, by, bg, respectively output by the controller of A and B Road, red, yellow, green signal light eg, ey, er, respectively, by the control of the controller output 25S, 5S, 20S, three timer enable signal.
Packet file list
(Preview for download)
trafficlight\control.bsf
............\control.vhd
............\db\add_sub_jlh.tdf
............\..\add_sub_llh.tdf
............\..\trafficlight.asm.qmsg
............\..\trafficlight.cbx.xml
............\..\trafficlight.cmp.cdb
............\..\trafficlight.cmp.hdb
............\..\trafficlight.cmp.qrpt
............\..\trafficlight.cmp.rdb
............\..\trafficlight.cmp.tdb
............\..\trafficlight.cmp0.ddb
............\..\trafficlight.dbp
............\..\trafficlight.db_info
............\..\trafficlight.eco.cdb
............\..\trafficlight.eds_overflow
............\..\trafficlight.fit.qmsg
............\..\trafficlight.fnsim.cdb
............\..\trafficlight.fnsim.hdb
............\..\trafficlight.fnsim.qmsg
............\..\trafficlight.hier_info
............\..\trafficlight.hif
............\..\trafficlight.map.cdb
............\..\trafficlight.map.hdb
............\..\trafficlight.map.qmsg
............\..\trafficlight.pre_map.cdb
............\..\trafficlight.pre_map.hdb
............\..\trafficlight.psp
............\..\trafficlight.rtlv.hdb
............\..\trafficlight.rtlv_sg.cdb
............\..\trafficlight.rtlv_sg_swap.cdb
............\..\trafficlight.sgdiff.cdb
............\..\trafficlight.sgdiff.hdb
............\..\trafficlight.sim.hdb
............\..\trafficlight.sim.qmsg
............\..\trafficlight.sim.qrpt
............\..\trafficlight.sim.rdb
............\..\trafficlight.sim.vwf
............\..\trafficlight.sld_design_entry.sci
............\..\trafficlight.sld_design_entry_dsc.sci
............\..\trafficlight.smp_dump.txt
............\..\trafficlight.syn_hier_info
............\..\trafficlight.tan.qmsg
............\time20.bsf
............\time20.vhd
............\time25.bsf
............\time25.vhd
............\time5.bsf
............\time5.vhd
............\trafficlight.asm.rpt
............\trafficlight.bdf
............\trafficlight.done
............\trafficlight.fit.eqn
............\trafficlight.fit.rpt
............\trafficlight.fit.summary
............\trafficlight.flow.rpt
............\trafficlight.map.eqn
............\trafficlight.map.rpt
............\trafficlight.map.summary
............\trafficlight.pin
............\trafficlight.pof
............\trafficlight.qpf
............\trafficlight.qsf
............\trafficlight.qws
............\trafficlight.sim.rpt
............\trafficlight.sof
............\trafficlight.tan.rpt
............\trafficlight.tan.summary
............\trafficlight.vhd
............\trafficlight.vwf
............\db
trafficlight
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