Search - traffic Signal and System

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[VHDL-FPGA-Verilog] jiaotongdeng DL : 0: 以FPGA为开发平台的交通信号系统，带有倒计时和蜂鸣器功能。-To FPGA development platform for the traffic signal system, with a countdown and the buzzer function.
Date : 2026-01-10 Size : 1kb User : AJ
[VHDL-FPGA-Verilog] t33 DL : 0: 交通灯控制系统某路口有一条主干道和一条支干路交叉而成。根据统计，主干道的交通流量为支路的两倍。要求： 1)、正常情况下，两路轮流放行，且主干道的放流时间是支路的两倍。信号转换时，按照以下规律显示：从通行变为停止时，按绿→黄→红次序变化；从停止变为通行时，按红→闪动→绿次序变化；主干道与支路的显示必须保证它们是交叉进行的。 2)、当路上出现特种车辆(如警车、消防车等)时，该路口应将它立即放行，并使另一方向停止。如果两个方向同时出现特种车，应时主干道的车辆先放行。-Traffic light control system A main road and a junction with a cross made of branches trunks. According to Commission Meter, main road traffic to slip twice. Requirements: 1), under normal circumstances, release of two turns, and the main road of releasing time Is the branch twice. Signal conversion, the following rule shows: From the passage into a stop, press the green → yellow → red sequence changes Into a passage from the stop, press the flashing red → green → order changes Trunk and branch display must ensure that they are interleaved. 2), when on the road there special vehicles (such as police cars, fire engines, etc.), the Road Mouth it should be released immediately, and to stop the other direction. If the two directions At the same time there special vehicles, seasonal vehicles first release trunk
Date : 2026-01-10 Size : 2kb User : 胡芳洲
[VHDL-FPGA-Verilog] gtd DL : 0: 近年来，随着交通流量的日益增大，在城市道路上为了缓和行人过马路时车辆与行人争抢道路这一矛盾，在一些行人过马路比较集中的路段如学校、商场等门口的人行横道上加装了人行横道信号灯。本系统采用单片机AT89C51为核心器件来设计开发交通灯控制器，设计开发人行横道交通灯系统，使系统实用性更强、操作更为简单。 1.在人流量不很多的时候，黄色信号灯以1s闪烁，提醒车辆慢行通过，行人确保安全下通过。 2.在放学、下班、节假日人流量高峰期，按下信号灯的控制按钮，交通灯信号系统时序工作。-In recent years, with the increasing traffic flow, on the road in the city to ease pedestrian crossing the road when vehicles and pedestrians compete for this contradiction, in a number of pedestrians crossing the road sections are concentrated, such as schools, shopping malls, etc. on the front of the crosswalk installation of a crosswalk signal. The system uses the microcontroller AT89C51 as the core design and development of devices to control traffic lights, traffic lights crosswalk system design and development, to make the system more practical, easier operation. 1 the flow of people without a lot of time, the yellow lights flashing to 1s, to remind the vehicle slowly passed through the pedestrians to ensure safety. 2 in school, work, holidays, peak flow of people, press the control button lights, traffic light signal system timing work.
Date : 2026-01-10 Size : 62kb User : 刘清源
[VHDL-FPGA-Verilog] trafficlight DL : 0: 基于VHDL的十字路口交通灯控制系统设计与实现,定时器模块由25S、5S、20S三个定时器组成，分别确定相应信号灯亮的时间。三个定时器采用以秒脉冲为时钟的计数器实现。eg、ey、er分别是三个定时器的工作使能信号，tm25、tm5、tm20是三个定时器的计数结束指示信号。控制模块是对系统工作状态的转换进行控制，根据交通规则可得系统状态转换情况。ar、ay、ag br、by、bg分别表示由控制器输出的A道和B道的红、黄、绿信号灯亮的时间；eg、ey、er分别表示由控制器输出的控制25S、5S、20S三个定时器的工作使能信号。-Based on VHDL crossroads traffic lights control system design and implementation, the timer module from 25S, 5S, 20S, three timer composition, respectively, to determine the corresponding signal light time. Three timer a second pulse of the clock counter. eg, ey, er, respectively, three timer enable signal tm25, tm5, of tm20 the end of the three timers count indication signal. The control module to control the conversion of the system working state conversions in accordance with the rules of the road can get system status. ar, ay, ag br, by, bg, respectively output by the controller of A and B Road, red, yellow, green signal light eg, ey, er, respectively, by the control of the controller output 25S, 5S, 20S, three timer enable signal.
Date : 2026-01-10 Size : 181kb User : 蔡利波
[VHDL-FPGA-Verilog] traffic_Light DL : 0: 模拟十字路口交通灯的VHDL程序，附有用与配合ModelSim的仿真程序。内容：交通灯设计（1）A，B方向各有红，黄，绿灯，初始态全为红灯，之后东西方向通车，绿灯灭后，黄灯闪烁，各路口通车时间为30秒，由两个七段数码管计数，当显示时间小于3秒的时候通车方向黄灯闪烁（2）系统时钟1KHz，黄灯闪烁时钟要求为2Hz，七段码管的时间显示为1Hz脉冲，即1秒递减一次，在显示时间小于3秒时，通车方向的黄灯以2Hz的频率闪烁，系统中加入外部复位信号。（3）用ModelSim做仿真 -VHDL program simulate the crossroads of traffic lights, accompanied with the ModelSim simulation program. : Traffic light design (1) A, B, the direction of each red, yellow, green, and the initial state of all the red, the east-west direction after the opening of the green off, flashing yellow light, the intersection open to traffic for 30 seconds by two seven segment LED count, (2) the opening of the direction of the yellow light flashes when the display time is less than 3 seconds when the system clock 1KHz, flashing yellow light clock requirements for 2Hz, seven segment tubes 1Hz pulse, that is a seconds, decreasing the display time of less than 3 seconds, the opening direction of the yellow light is flashing, the system by adding an external reset signal frequency of 2Hz. (3) with ModelSim simulation
Date : 2026-01-10 Size : 1kb User : 陈若耿
[VHDL-FPGA-Verilog] jtd DL : 0: 十字路口车辆穿梭，行人熙攘，车行车道，人行人道，有条不紊。那么靠什么来实现这井然秩序呢？靠的就是交通信号灯的自动指挥系统。交通信号灯控制方式很多。本系统采用MCS-51系列单片机AT89C51为中心器件来设计交通灯控制器，实现了能根据实际车流量通过8051芯片的P3口设置红、绿灯燃亮时间的功能；红绿灯循环点亮，倒计时剩5秒时黄灯闪烁警示（交通灯信号通过P1口输出，显示时间通过P0口输出至双位数码管）。本系统设计周期短、可靠性高、实用性强、操作简单、维护方便、扩展功能强。 -The intersection vehicles shuttle, the pedestrian is bustling, car dealership traffic lane, person sidewalk, methodical. Then depending on what to realizes this orderly order? the traffic lights on the automatic control system. There are great number kinds of modes to control the traffic lights. The system uses a series of MCS-51 as the center AT89C51 single-chip device designed to control the traffic lights, so as to realize the function of setting red, green light time by 8051 chip’s P3 port according to the actual traffic flows, lighting the red-light and green-light by turn and lighting the yellow-light to warm while 5 seconds left(outputting the traffic light signal by P1,outpuing the time by P0 and showing the time on double-digits nixie tube). Short of the design cycle, high reliability, practical, simple operation, easy maintenance, the expansion of powerful is this system.
Date : 2026-01-10 Size : 23kb User : 何健
[VHDL-FPGA-Verilog] code DL : 0: 通过对十字路口交通灯控制系统的设计，掌握不同进制计数归零的描述方法以及通过信号使进程进行相互通信的方法。-Through the intersection traffic light control system design, master describes different methods to zero and the decimal counting processes via signal to communicate with each method.
Date : 2026-01-10 Size : 1kb User : 张双图
[VHDL-FPGA-Verilog] traffic-light DL : 0: （1） Divid 模块：1Hz 分频模块，开发板提供50MHz 的系统时钟，而该设计交通灯转换以秒为计时单位，对50MHz 分频得到1Hz 脉冲信号。（2） Divid_200 模块: 200Hz 分频模块,用于产生动态扫描模块的时钟。一个数码管稳定显示要求的切换频率要大于50Hz，那么4 个数码管则需要50×4＝200Hz 以上的切换频率才能看到不闪烁并且持续稳定显示的字符，因而扫描频率设定为 200Hz。（3） Control 模块：A、B 方向红绿灯控制模块，红灯、绿灯为20 秒，黄灯为5 秒。并实现计时数据转换，即将数据分为十位显示数据，与各位显示数据，用于数码管显示。（4） saomiao 扫描模块：轮流选通2 位数码管，实现动态扫描，以显示倒计时数据。-(1) Divid module: 1Hz divider module, the development board provides 50MHz system clock, and the design of traffic lights Conversion in seconds for the time unit, the 50MHz frequency to be 1Hz pulse signal. (2) Divid_200 module: 200Hz frequency division module, used to generate the dynamic scanning module clock. A digital tube Stable display requirements of the switching frequency is greater than 50Hz, then the four digital tubes need 50 × 4 200Hz or more Of the switching frequency to see the non-flickering and continuous display of the characters, so the scanning frequency is set to 200Hz. (3) Control module: A, B direction traffic light control module, red, green for 20 seconds, yellow for 5 seconds. And to achieve timing data conversion, the data is divided into ten display data, and you display data for digital display. (4) saomiao scanning module: 2-bit strobe digital control, dynamic scanning to show the countdown data.
Date : 2026-01-10 Size : 521kb User : panda