Search - simulink

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[VHDL-FPGA-Verilog] FSKDFSK DL : 1: fsk调制与解调，此程序经过验证，可以运用，通讯方面的同学可以用-FSK modulation and demodulation, this procedure has been verified and can use communications students can use
Date : 2026-01-01 Size : 3kb User : we
[VHDL-FPGA-Verilog] pwm-20010309[1].tar DL : 0: PWM产生程序，绝对经典，好就顶一下先，谢谢了-PWM a process absolute classics, and what good on top first, I thank the
Date : 2026-01-01 Size : 148kb User : 刘佛印
[VHDL-FPGA-Verilog] ver-fir-coefficient DL : 0: vhdl source,ver-fir-coefficient,simulink of fir with soft ware input
Date : 2026-01-01 Size : 390kb User : heti
[VHDL-FPGA-Verilog] simulink-03-31 DL : 0: 基于MATLAB/DSP Ｂuild可控信号发生器，由Ｍatlab建模综合，并生成ＶＨＤＬ代码，由Ｑuartus编译通过．-Based on MATLAB/DSP Build controllable signal generator, by the Matlab modeling synthesis, and generates VHDL code, adopted by the Quartus compiler.
Date : 2026-01-01 Size : 291kb User : ltianyang
[VHDL-FPGA-Verilog] add_rounding DL : 0: 一个基于Matlab+Simulink的带Rounding功能的加法器实现-Based on Matlab+ Simulink with Rounding adder functions realize
Date : 2026-01-01 Size : 9kb User : QU YIFAN
[VHDL-FPGA-Verilog] complex_add DL : 0: 一个基于Matlab+Simulink的复数加法器实现-Based on Matlab+ Simulink plural adder realize
Date : 2026-01-01 Size : 8kb User : QU YIFAN
[VHDL-FPGA-Verilog] MyState DL : 0: 这份是实验课上的教师和学生用的实例。关于用matlab simulink仿真状态机并生成vhdl代码的详细内容-The experimental class teachers and students to use examples. Matlab simulink simulation on the use of state machine and generates VHDL code details
Date : 2026-01-01 Size : 946kb User : 张三
[VHDL-FPGA-Verilog] pll DL : 0: 模拟锁相环（apll）的一些simulink模型-Analog phase-locked loop (apll) some simulink model
Date : 2026-01-01 Size : 717kb User : prescaler
[VHDL-FPGA-Verilog] lab1 DL : 0: system generator/simulink 应用开发实例，User Starting
Date : 2026-01-01 Size : 151kb User : troy
[VHDL-FPGA-Verilog] lab4 DL : 0: system generator/simulink 应用开发4，User Starting
Date : 2026-01-01 Size : 118kb User : troy
[VHDL-FPGA-Verilog] cic DL : 0: 在MATLAB2007A/SIMULINK环境下用DSP BUILDER8.0实现了五级CIC，解决了溢出问题。生成了可用的VHDL文件。- DSP BUILDER8.0 A 5 stages CIC filer is realized in MATLAB2007A/SIMULINK by using DSP Builder 8.0.The overflow problem is resulved.Useful VHDL files are generated at last.
Date : 2026-01-01 Size : 1.47mb User : hcq
[VHDL-FPGA-Verilog] qpsk_simulink DL : 0: Matlab simulink qpsk
Date : 2026-01-01 Size : 7kb User : mmurali
[VHDL-FPGA-Verilog] HDLImplementationoftheVariableStepSize DL : 0: proposes a Verilog implementation of the Normalized Least Mean Square (NLMS) adaptive algorithm, having a variable step size. The envisaged application is the identification of an unknown system. First the convergence of derived LMS algorithms was analyzed in a Simulink application.
Date : 2026-01-01 Size : 218kb User : 陳柏宇
[VHDL-FPGA-Verilog] QAM16_demo DL : 0: This a demonstration for 16QAM. It is a Simulink model, including hardware implementation on Xilinx FPGA for adaptive equalizer and carrier recovery. -This is a demonstration for 16QAM. It is a Simulink model, including hardware implementation on Xilinx FPGA for adaptive equalizer and carrier recovery.
Date : 2026-01-01 Size : 44kb User : 徐滨
[VHDL-FPGA-Verilog] Simulink-to-VHDL-Route DL : 0: This paper presents the way of speeding up the route from the oretical design with Simulink/Matlab, via behavioral simulation in fixed-point arithmetic to the implementation on either FPGA or custom silicon. This has been achieved by porting the netlist of the Simulink system description into the VHDL. At the first instance, the Simulink-to-VHDL converter has been designed to use structural VHDL code to describe system interconnections, allowing simple behavioral descriptions for basic blocks. The resulting VHDL code delivers bit-true result when compared to the equivalent fixed-point Simulink model simulations.-This paper presents the way of speeding up the route from the theoretical design with Simulink/Matlab, via behavioral simulation in fixed-point arithmetic to the implementation on either FPGA or custom silicon. This has been achieved by porting the netlist of the Simulink system description into the VHDL. At the first instance, the Simulink-to-VHDL converter has been designed to use structural VHDL code to describe system interconnections, allowing simple behavioral descriptions for basic blocks. The resulting VHDL code delivers bit-true result when compared to the equivalent fixed-point Simulink model simulations.
Date : 2026-01-01 Size : 144kb User : jack
[VHDL-FPGA-Verilog] 3813412-Matlab-Simulink-Simulink-Matlab-to-Vhdl.r DL : 0: Simulink/Matlab-to-VHDL Route for Full-Custom/FPGA Rapid Prototyping of DSP Algorithms
Date : 2026-01-01 Size : 144kb User : T. H. Sutikno
[VHDL-FPGA-Verilog] 16qam DL : 0: simulink平台上实现16QAM的解调模型，并用XILINX ISE软件实现modesim仿真-Simulink on a platform of 16QAM demodulation models, modesim and XILINX ISE software simulation
Date : 2026-01-01 Size : 48kb User : 张德
[VHDL-FPGA-Verilog] simulink-matlab-to-vhdl DL : 0: convert matlab and simulink files to vhdl
Date : 2026-01-01 Size : 177kb User : tatta
[VHDL-FPGA-Verilog] DDS DL : 0: 这个是在quartusii和matlab simulink下搭的dds的模型，已经经过仿真是可以的。并且已经转为vhdl代码。-This is quartusii and matlab simulink model to catch the dds, has been the simulation is possible. And has to vhdl code.
Date : 2026-01-01 Size : 1.23mb User : jiang
[VHDL-FPGA-Verilog] modelism-simulink DL : 0: Modelsim simulation elementary guidance -Modelsim simulation elementary guidance
Date : 2026-01-01 Size : 225kb User : 松竹

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