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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 1.47mb
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  • Author :h****
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Introduction - If you have any usage issues, please Google them yourself
DSP BUILDER8.0 A 5 stages CIC filer is realized in MATLAB2007A/SIMULINK by using DSP Builder 8.0.The overflow problem is resulved.Useful VHDL files are generated at last.
Packet file list
(Preview for download)
cic\001_5级CIC时有溢出_未查明原因.jpg
...\005_5级CIC时有溢出_未查明原因1signal_2CicOut_3IntegralOut.jpg
...\500_5级CIC时无溢出_输入均值必须为0.jpg
...\501_signal_spectrum_10kAnd1M.jpg
...\502_CICout_spectrum_10kAnd1M.jpg
...\cic.mdl
...\cic_error_model.mdl
...\....quartus\db\in_bus_extend.db_info
...\...........\..\in_bus_extend.eco.cdb
...\...........\..\in_bus_extend.sld_design_entry.sci
...\...........\in_bus_extend.qpf
...\...........\in_bus_extend.qsf
...\...........\in_bus_extend.qws
...\...........\in_bus_extend.vhd
...\cic_test.mdl
...\cic_test_unsigned.mdl
...\cic_test_unsigned_5stage.ipx
...\cic_test_unsigned_5stage.mdl
...\cic_test_unsigned_5stage.mdlxml
...\cic_test_unsigned_5stage.qip
...\cic_test_unsigned_5stage_add.tcl
...\.........................dspbuilder\cic_test_unsigned_5stage.asm.rpt
...\...................................\cic_test_unsigned_5stage.fit.rpt
...\...................................\cic_test_unsigned_5stage.fit.smsg
...\...................................\cic_test_unsigned_5stage.fit.summary
...\...................................\cic_test_unsigned_5stage.flow.rpt
...\...................................\cic_test_unsigned_5stage.map.rpt
...\...................................\cic_test_unsigned_5stage.map.summary
...\...................................\cic_test_unsigned_5stage.pin
...\...................................\cic_test_unsigned_5stage.pof
...\...................................\cic_test_unsigned_5stage.qpf
...\...................................\cic_test_unsigned_5stage.qsf
...\...................................\cic_test_unsigned_5stage.sdc
...\...................................\cic_test_unsigned_5stage.sof
...\...................................\cic_test_unsigned_5stage.sta.rpt
...\...................................\cic_test_unsigned_5stage.sta.summary
...\...................................\db\add_sub_h2i.tdf
...\...................................\..\add_sub_i3i.tdf
...\...................................\..\alt_dspbuilder_AROUND.vhd
...\...................................\..\alt_dspbuilder_ASAT.vhd
...\...................................\..\alt_dspbuilder_BarrelShiftAltr.vhd
...\...................................\..\alt_dspbuilder_barrelshifter.jvgen_cache.xml
...\...................................\..\alt_dspbuilder_barrelshifter.vhd
...\...................................\..\alt_dspbuilder_barrelshifter_GNFP3FIE2D.vhd
...\...................................\..\alt_dspbuilder_cast.jvgen_cache.xml
...\...................................\..\alt_dspbuilder_cast.vhd
...\...................................\..\alt_dspbuilder_cast_GNC6JBRIPW.vhd
...\...................................\..\alt_dspbuilder_cast_GNMZU2DRLG.vhd
...\...................................\..\alt_dspbuilder_cast_GNNV6K367I.vhd
...\...................................\..\alt_dspbuilder_cast_GNSATDB35T.vhd
...\...................................\..\alt_dspbuilder_clock.jvgen_cache.xml
...\...................................\..\alt_dspbuilder_clock.vhd
...\...................................\..\alt_dspbuilder_clock_GNEX65AQCL.vhd
...\...................................\..\alt_dspbuilder_clock_GNXPOFXHLB.vhd
...\...................................\..\alt_dspbuilder_constant.jvgen_cache.xml
...\...................................\..\alt_dspbuilder_constant.vhd
...\...................................\..\alt_dspbuilder_constant_GN5VNYBYHM.vhd
...\...................................\..\alt_dspbuilder_delay.jvgen_cache.xml
...\...................................\..\alt_dspbuilder_delay.vhd
...\...................................\..\alt_dspbuilder_delay_GNM4LG35IK.vhd
...\...................................\..\alt_dspbuilder_delay_GNSJG6JESL.vhd
...\...................................\..\alt_dspbuilder_delay_GNTK2YXDN5.vhd
...\...................................\..\alt_dspbuilder_delay_GNZGCR47RM.vhd
...\...................................\..\alt_dspbuilder_parallel_adder.jvgen_cache.xml
...\...................................\..\alt_dspbuilder_parallel_adder.vhd
...\...................................\..\alt_dspbuil
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