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[VHDL-FPGA-Verilog] dianzizhong DL : 0: (1) 设置复位功能　　 (2) 设置启/停功能　　 (3) 计时精度大于0.01s 　　 (4) 最长计时时间为24h （5）闹钟（6）设定时间（7）正点报时 -(1) set the reset function (2) set up Kai/stop function (3) is greater than the accuracy time 0.01s (4) the longest time to time 24h (5) the alarm (6) set the time (7) punctual time
Date : 2025-12-26 Size : 1mb User : 孙国栋
[VHDL-FPGA-Verilog] daima DL : 0: 用VHDL语言设计一个数字秒表： 1、秒表的计时范围是0秒~59分59.99秒，显示的最长时间为59分59秒。 2、计时精度为10MS。 3、复位开关可以随时使用，按下一次复位开关，计时器清零。 4、具有开始/停止功能，按一下开关，计时器开始计时，再按一下，停止计时。系统设计分为几大部分，包括控制模块、时基分频模块、计时模块和显示模块等。其中，计时模块有分为六进制和十进制计时器。计时是对标准时钟脉冲计数。计数器由四个十进制计数器和两个六进制计数器构成，其中毫秒位、十毫秒位、秒位和分位用十进制计数器，十秒位和十分位用六进制计数器。计时显示电路时将计时值在LED上七段数码管上显示出来。计时电路产生的计时值经过BCD七段码后，驱动LED数码管。-With VHDL language design digit stopwatch: 1, Stopwatch s time scope is 0 second ~59 minute 59.99 second, the demonstration longest time is 59 minute 59 second. 2, The time precision is 10MS. 3, The reset switch may momentarily use, presses down a reset switch, the timer reset. 4, Has starts/the stop function, according to the switch, the timer starts to time, presses again, stops timing. The system design divides into several major parts, including control module, time base frequency division module, time module and display module and so on. And, the time module influentials for the senary and the decimal base timer. The time is to the standard clock pulse counting. Counter by four decade counters and two senary counter constitution, a millisecond position, ten milliseconds positions, a second position and the rank with the decade counter, ten second position and ten ranks use the senary counter. When time display circuit will time the value on the nixietube to demonstrate on LED. The
Date : 2025-12-26 Size : 5kb User : SAM
[VHDL-FPGA-Verilog] stopwatch DL : 0: 基于vhdl的数字秒表，计时精度为1/100秒，最长计时时间为59分59.59秒；设有复位开关、起停开关；验证可用。-On vhdl digital stopwatch, timing accuracy of 1/100 seconds, the longest time time of 59 minutes 59.59 seconds with reset switch, start-stop switches validation is available.
Date : 2025-12-26 Size : 260kb User : ly
[VHDL-FPGA-Verilog] GOLD_VHDL DL : 0: 论文讨论的是基于VHDL 实现在系统编程平衡GOLD 码逻辑电路设计，给出周期与相位可编程平衡GOLD 码生成电路设计方案。该方案由最长线性移位寄存器与可选反馈支路构成。-Discussion paper is based on VHDL programming to achieve a balance in the system logic circuit design GOLD code given cycle and phase balance GOLD programmable code generation circuit design. The program consists of the longest linear feedback shift register with the optional slip form.
Date : 2025-12-26 Size : 106kb User : wendy
[VHDL-FPGA-Verilog] program DL : 0: 1/100s计时器的FPGA实现，本设计的计时器能实现显示最长计时时间为1分59.99秒，且精度大于1/100s，计时器能显示1/100s的时间.-1/100s timer FPGA, the design of the timer to achieve the longest time show time of 1 minutes, 59.99 seconds, and the precision is greater than 1/100s, 1/100s timer can display the time.
Date : 2025-12-26 Size : 534kb User : sword
[VHDL-FPGA-Verilog] startstopwatch DL : 0: 运动计时器的设计（1）在四个七段LED数码管上显示分钟和秒，最长的计时时间为59：59。（2）按下清零按键，在四个七段LED数码管上显示的时间为00：00。（3）按下启动/暂停按键，则启动或暂停计时器计时。其功能与实际的计时器的开始/停止按钮功能相同。设计一个能显示分、秒的计时器。在四个七段LED数码管上显示出来。-Sports timer design (1) in the four seven-segment LED digital display minutes and seconds, the longest time was 59:59 time. (2) Press the Clear button in the four seven-segment LED digital display time for 00:00. (3) Press the Start/Pause button, start or pause the timer clock. The timer function and the actual start/stop button to function the same. Design a display minutes and seconds timer. In four seven-segment LED digital tube display.
Date : 2025-12-26 Size : 1kb User : 吴凡
[VHDL-FPGA-Verilog] digit-traffic-light DL : 0: 某交通管理部门要求，交通灯要求主干道绿灯至少保持2分钟（其中不包括绿灯闪烁时间），在此前提下，当支路检测到有车或人时，主干道绿灯闪烁3秒，然后黄灯持续亮3秒，红灯再亮，同时支路绿灯亮，红灯灭。当支路连续5秒检测不到车和人时，支路绿灯闪烁3秒，然后黄灯持续亮3秒，红灯再亮，同时主干道绿灯亮，红灯灭，支路绿灯最长持续20秒（不包括绿灯闪烁时间）。若从绿灯闪烁开始禁止支路上行人和车辆通行，则可保证主干道禁止通行的最长时间为26秒。支路可通过仪器来检测有无车辆和行人，对于行人，由于其不定性，需要设置一些仪器，如果有行人想通过，需站在其中一个检测仪下，当任一仪器检测到有车辆和行人要横穿主干道时，发出信号。由于主干道禁止通行的时间至多为26秒，因此，无需检测有无车辆和行人。- Requirements of a traffic management department, asked the main road traffic lights green for at least 2 minutes (not including the green light flashes the time), in this context, when the slip road vehicle or person is detected, the main road the green light flashes for 3 seconds, then yellow lamp is lit for 3 seconds, then red light, green light at the same time slip, red light off. When the slip is not detected continuously for 5 seconds when the cars and people, slip the green light flashes for 3 seconds, and then the yellow light is lit for 3 seconds, then red light, green light while the main road, the red light off, the longest continuous green slip 20 seconds (not including the green flashing light). If the green light flashes from a ban on pedestrian and vehicle traffic support on the road, you can ensure that the maximum time the main road closed to traffic for 26 seconds. Slip through the instrument to detect whether the vehicles and pedestrians, the pedestrians, because o
Date : 2025-12-26 Size : 203kb User : jamesheller
[VHDL-FPGA-Verilog] division3f DL : 0: 三分频电路的Verilog实现。2N分频很容易，但是奇数分频电路较为复杂一些，也是做数字电路面试最长问道的问题之一。-Third frequency circuits Verilog implementation. 2N frequency is easy, but the odd frequency circuit is less complex, also in the digital circuit of the longest interview questions asked.
Date : 2025-12-26 Size : 4kb User : chenhaoc
[VHDL-FPGA-Verilog] 2 DL : 0: 设计一个具有时、分、秒计时的电子钟，按24小时计时。要求：（1）数字钟的时间用六位数码管分别显示时、分、秒；（2）用两个控制键，对数字钟分别进行分、时校正；（3）具有仿广播电台整点报时的功能。即每逢59分51秒、53秒、55秒及57秒时，发出4声500Hz低音，在59分59秒时发出一声1kHz高音，它们的持续时间均为1秒。最后一声高音结束的时刻恰好为正点时刻。（4）具有定时闹钟功能，且最长闹铃时间为1分钟。要求可以任意设置闹钟的时、分；闹铃信号为500Hz和1kHz的方波信号，两种频率的信号交替输出，且均持续1秒。设置一个停止闹铃控制键，可以停止输出闹铃信号。（5）输入时钟脉冲的频率为50MHz。(Design an electronic clock with time, minutes and seconds, and time by 24 hours. Requirements: (1) the time of digital clock is shown with six digital tubes, respectively, minutes and seconds; (2) two control keys are used to divide and adjust the digital clock respectively. (3) it has the function of imitating radio station. That means that at 59 minutes, 51 seconds, 53 seconds, 55 seconds and 57 seconds, a 4 500Hz bass is emitted. A 1kHz note is emitted at 59 minutes 59 seconds, and their duration is 1 second. The end of the last treble is exactly the moment of truth. (4) it has a timer function and the longest alarm time is 1 minute. Ask to set the alarm clock at any time. The alarm signal is a square wave signal of 500Hz and 1kHz. The signals of both frequencies alternate and output for one second. Set a stop alarm button to stop the output alarm signal. (5) the frequency of input clock pulse is 50MHz.)
Date : 2025-12-26 Size : 51kb User : LIMBO2K