With VHDL language design digit stopwatch: 1, Stopwatch s time scope is 0 second ~59 minute 59.99 second, the demonstration longest time is 59 minute 59 second. 2, The time precision is 10MS. 3, The reset switch may momentarily use, presses down a reset switch, the timer reset. 4, Has starts/the stop function, according to the switch, the timer starts to time, presses again, stops timing. The system design divides into several major parts, including control module, time base frequency division module, time module and display module and so on. And, the time module influentials for the senary and the decimal base timer. The time is to the standard clock pulse counting. Counter by four decade counters and two senary counter constitution, a millisecond position, ten milliseconds positions, a second position and the rank with the decade counter, ten second position and ten ranks use the senary counter. When time display circuit will time the value on the nixietube to demonstrate on LED. The

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.....\bcd7.vhd
.....\cb10.vhd
.....\cdu10.vhd
.....\cdu6.vhd
.....\count.vhd
.....\ctrl.vhd
.....\ctrltest.vhd
.....\DecL7s.vhd
.....\mb.vhd
.....\mulx.vhd

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