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[VHDL-FPGA-Verilog] jtag0 DL : 0: 本程序使用vhdl编写的jtag接口实现程序,其中有些功能未能实现,希望有人能够帮忙完善!-vhdl the procedures used to prepare the jtag interface procedures, which some of them did not materialize, hope someone can help perfect!
Date : 2025-12-25 Size : 84kb User : 马斌
[VHDL-FPGA-Verilog] usb_cpld_code DL : 0: usb_cpld_code.zip usbjtag - Variations on the implementation of a USB JTAG adapter.-usb_cpld_code.zip usbjtag-o Variations n the implementation of a USB JTAG adapter.
Date : 2025-12-25 Size : 26kb User : david
[VHDL-FPGA-Verilog] usb_jtag-20070128-1751 DL : 0: 网上流传的usb_blaster原理图里的CPLD源码,主要是实现usb时序转换成JATG时序输出！-spreading online usb_blaster tenets of the CPLD Ituri source, usb key is timing converted into JATG sequential output!
Date : 2025-12-25 Size : 51kb User : 冯海
[VHDL-FPGA-Verilog] verilog_usbblaster DL : 0: 用verilog编写的USB下载线程序实现USB协议和JTAG接口的数据转换实现状态机-Verilog prepared using USB download cable program realize USB protocol and JTAG interface to achieve data conversion state machine
Date : 2025-12-25 Size : 1.5mb User : 一王
[VHDL-FPGA-Verilog] jtag_logic DL : 0: 这是自制altera usb_blaster所用到的CPLD程序，用VHDL语言写的。
Date : 2025-12-25 Size : 2kb User : wdy2004
[VHDL-FPGA-Verilog] USB_jtag DL : 0: 用verilog编写的USB下载线程序实现USB协议和JTAG接口的数据转换实现状态机。-Verilog prepared using USB download cable program realize USB protocol and JTAG interface to achieve data conversion state machine.
Date : 2025-12-25 Size : 1.5mb User : 霍飘摇
[VHDL-FPGA-Verilog] usb_jtag DL : 0: FPGA、CPLD芯片的usb数据下载线，下载速度是并口的5位，内有原理图用程序-FPGA, CPLD chip usb data download lines, download speed is the parallel port of the five, with a schematic diagram of procedures in
Date : 2025-12-25 Size : 229kb User : 李聚光
[VHDL-FPGA-Verilog] usb-driver DL : 0: Xilinx USB下载线 Linux驱动，支持原来并口线，以及现在USB线，最重要的是支持基于FT2232的简易USB JTAG，FT2232不仅可以通过OpenOCD调ARM，还可以下载Xilinx FPGA了！-linux driver of Xilinx USB Platform cable, support xilinx usb cable and parallel cable, in addition, it support usb jtag based on FT2232!
Date : 2025-12-25 Size : 25kb User : gxliu
[VHDL-FPGA-Verilog] usb DL : 0: 程序说明: 本次实验控制开发板USB，与PC机进行通信，并在显示字符。目录说明: 工程在\project文件夹里面源文件和管脚分配在\rtl文件夹里面下载文件在\download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。-Procedure Note: In this experiment, control development board USB, and PC, to communicate, and display character. Catalog Description: The project \ project folder inside the source file and pins distributed in \ rtl folder inside download the file in the \ download folder inside,. Mcs for the PROM mode download files,. Bit for the JTAG debug download the file.
Date : 2025-12-25 Size : 79kb User : 军军
[VHDL-FPGA-Verilog] usb_jtag DL : 0: usb通过Jtag口进行下载的源码程序，可以方便的通过它下载到EPROM里面-usb port for downloading through the Jtag source programs can be easily downloaded to the EPROM which through its
Date : 2025-12-25 Size : 97kb User : 邓旺波
[VHDL-FPGA-Verilog] Alterafpga_jtag DL : 0: Altera FPAG USB jtag下载线制作资料,对制作及学习很有用-Altera FPAG USB jtag download cable production data, production and learning useful
Date : 2025-12-25 Size : 2.25mb User : 磊
[VHDL-FPGA-Verilog] Oscilloscope DL : 0: The design is designed partly in VHDL, partly in schematic drawings and targets a Xilinx Spartan-2E FPGA. However, since the design was tailored specifically for the aforementioned boards it is highly unlikely that it can be ported to other hardware. The circuits were designed on a Windows XP using the Xilinx WebPack 6.2 tool. The transfer of the design to the FPGA was carried out either with the Xilinx Impact tool through a parallel JTAG cable or with the Digilent Export utility through a USB JTAG cable.
Date : 2025-12-25 Size : 1.77mb User : sami
[VHDL-FPGA-Verilog] Quartus_II_Project DL : 0: Date : 2025-12-25 Size : 466kb User : 陶宇
[VHDL-FPGA-Verilog] DE2_USB_API DL : 0: This design contains hardware and software that allows you to test various components on the board, including the LEDs, 7-segment displays, SRAM, SDRAM, Flash, and the VGA port. All of this is done via a software interface running on your computer. The JTAG USB link on the board is used to communicate between the hardware circuit and the software program.
Date : 2025-12-25 Size : 1.5mb User : 马晓
[VHDL-FPGA-Verilog] usb-blaster DL : 1: FPGA的jtag下载线，适用于Actel系列。-FPGA-jtag download cable for Actel series.
Date : 2025-12-25 Size : 4.8mb User : 小熊
[VHDL-FPGA-Verilog] 1 DL : 1: 基于USB接口的边界扫描测试控制器设计,很实用，值得参考。-jtag tap controller
Date : 2025-12-25 Size : 375kb User : mojhui
[VHDL-FPGA-Verilog] lattice_usb_ft2232_cable_sch DL : 0: Lattice USB FT2232 JTAG Programming Cable Schematic
Date : 2025-12-25 Size : 237kb User : kaos_engr