JTAG emulator hardware implementation, the use of CPLD+ USB controller chip architecture. This is the JTAG CPLD implementation of the RTL source code.

Open_JTAG.map.rpt
Open_JTAG.tan.rpt
clock_mux.vhd
serializer.vhd
tap_sm.vhd
Open_JTAG.done
Open_JTAG.pin
Open_JTAG.pof
Open_JTAG.qsf
Open_JTAG.qws
Open_JTAG.fit.summary
Open_JTAG.map.summary
Open_JTAG.tan.summary
clock_mux.bsf
serializer.bsf
tap_sm.bsf
Open_JTAG.bdf
Open_JTAG.qpf
Main.vwf
Open_JTAG.vwf
serializer.vwf
tap_sm.vwf
db\logic_util_heursitic.dat
..\Open_JTAG.asm.qmsg
..\Open_JTAG.asm.rdb
..\Open_JTAG.asm_labs.ddb
..\Open_JTAG.cbx.xml
..\Open_JTAG.cmp.cdb
..\Open_JTAG.cmp.hdb
..\Open_JTAG.cmp.kpt
..\Open_JTAG.cmp.logdb
..\Open_JTAG.cmp.rdb
..\Open_JTAG.cmp.tdb
..\Open_JTAG.cmp0.ddb
..\Open_JTAG.db_info
..\Open_JTAG.eco.cdb
..\Open_JTAG.fit.qmsg
..\Open_JTAG.hier_info
..\Open_JTAG.hif
..\Open_JTAG.lpc.html
..\Open_JTAG.lpc.rdb
..\Open_JTAG.lpc.txt
..\Open_JTAG.map.cdb
..\Open_JTAG.map.hdb
..\Open_JTAG.map.logdb
..\Open_JTAG.map.qmsg
..\Open_JTAG.pre_map.cdb
..\Open_JTAG.pre_map.hdb
..\Open_JTAG.rtlv.hdb
..\Open_JTAG.rtlv_sg.cdb
..\Open_JTAG.rtlv_sg_swap.cdb
..\Open_JTAG.sgdiff.cdb
..\Open_JTAG.sgdiff.hdb
..\Open_JTAG.sld_design_entry.sci
..\Open_JTAG.sld_design_entry_dsc.sci
..\Open_JTAG.smart_action.txt
..\Open_JTAG.syn_hier_info
..\Open_JTAG.tan.qmsg
..\Open_JTAG.tis_db_list.ddb
..\Open_JTAG.tmw_info
incremental_db\compiled_partitions\Open_JTAG.root_partition.map.kpt
..............\README
Open_JTAG.asm.rpt
Open_JTAG.fit.rpt
Open_JTAG.flow.rpt
incremental_db\compiled_partitions
db
incremental_db

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