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[VHDL-FPGA-Verilog] zuosr8 DL : 0: Picasa 是Google提供的一个 Windows 应用程序；用户可以借助于该程序，在数秒钟内找到自己计算机上的图片，加以编辑并进行欣赏。-Picasa is the Google of a Windows application; Users can aid the process, in just a few seconds to find their own pictures on the computer, edit them and appreciate.
Date : 2026-01-11 Size : 3kb User : 孙潇
[VHDL-FPGA-Verilog] Oreilly.Programming.Google.App.Engine.Nov.2009.ra DL : 0: E-book: Oreilly.Programming.Google.App.Engine.Nov.2009
Date : 2026-01-11 Size : 3.01mb User : hank8617
[VHDL-FPGA-Verilog] Google_Earth-Labview DL : 0: 可以实时显示经纬度坐标，高程及utc时间，并将地标在google-earth卫星图上显示-Latitude and longitude coordinates, elevation and utc time can be displayed in real time, and landmarks in the satellite images on google-earth
Date : 2026-01-11 Size : 91kb User : lichunjie
[VHDL-FPGA-Verilog] booth_multiplier DL : 0: 从google上下载到的booth乘法器-booth multiplier
Date : 2026-01-11 Size : 91kb User : 徐云川
[VHDL-FPGA-Verilog] exp-CPU DL : 0: 实现简单的CPU通路，包括存储器、指令译码、多路选择器等功能部件-Simple CPU access （by google）
Date : 2026-01-11 Size : 854kb User : 丁丁
[VHDL-FPGA-Verilog] UART DL : 0: 在DE2开发板上实现串口收发设计，系统时钟频率为50MHz,reset信号低电平有效，输入数据最高位为1时按位取反再输出-Achieve serial transceiver design DE2 board, the system clock frequency of 50MHz, reset active low signal, the input data is the most significant bit is 1. Bitwise re-export Google 翻译（企业版）：译者工具包网站翻译器全球商机洞察关于 Google 翻译社区移动Google 大全隐私权和使用条款帮助发送反馈
Date : 2026-01-11 Size : 2kb User : zhangmin
[VHDL-FPGA-Verilog] vga DL : 0: This VHDL sample demonstrates how to generate a VGA signal to make it possible to connect an FPGA to a monitor. Written for Mimas v2, but probably easily adapted to any other board with a VGA connector on it (that can also be done by manually connecting a VGA port to a R-2R DAC and connecting that to GPIO: google for more information).
Date : 2026-01-11 Size : 1kb User : Ruben