Achieve serial transceiver design DE2 board, the system clock frequency of 50MHz, reset active low signal, the input data is the most significant bit is 1. Bitwise re-export Google 翻译（企业版）：译者工具包网站翻译器全球商机洞察 关于 Google 翻译社区移动Google 大全隐私权和使用条款帮助发送反馈

control.v
receiver.v
sender.v
top.v
UART_clock.v

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