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[VHDL-FPGA-Verilog] 基于FPGA的直接数字合成器设计 DL : 0: 1、利用FLEX10的片内RAM资源，根据DDS原理，设计产生正弦信号的各功能模块和顶层原理图； 2、利用实验板上的TLC7259转换器，将1中得到的正弦信号，通过D/A转换，通过ME5534滤波后在示波器上观察； 3、输出波形要求：在输入时钟频率为16KHz时，输出正弦波分辨率达到1Hz；在输入时钟频率为4MHz时，输出正弦波分辨率达到256Hz； 4、通过RS232C通信，实现FPGA和PC机之间串行通信，从而实现用PC机改变频率控制字，实现对输出正弦波频率的控制。-a use FLEX10-chip RAM resources, in accordance with DDS principle, design sinusoidal signal generated by the top-level functional modules and schematics; 2, the experimental board TLC7259 converters, will be a sinusoidal signal, the D/A conversion, after filtering through the ME5534 oscilloscope observation; 3, the output waveform requirements : the input clock frequency of 16KHz, sine wave output resolution of 1Hz; the input clock frequency of 4MHz, the sine wave output resolution of 256Hz; 4, RS232C communications, FPGA and PC serial communications between in order to achieve PC-frequency control characters, the realization of sine wave output frequency control.
Date : 2025-12-22 Size : 21kb User : 竺玲玲
[VHDL-FPGA-Verilog] dpram_fpga DL : 0: 这是我用vhdl语言，在fpga内部做了一个双口ram的程序。我的邮箱：wleechina@163.com-This is the language I used vhdl in fpga done an internal dual-port ram procedures. My mail : wleechina@163.com
Date : 2025-12-22 Size : 2.7mb User : 李伟
[VHDL-FPGA-Verilog] DDR_SDRAM_Controller DL : 0: DDR RAM控制器的VHDL源码，实现平台是Lattice FPGA，功能验证通过-DDR RAM controller VHDL source code, achieving the platform of Lattice FPGA, functional verification through
Date : 2025-12-22 Size : 662kb User : 钟方
[VHDL-FPGA-Verilog] FIFO_BEFORE DL : 0: 是基于fpga的FIFO乒乓操作，后面是与SDRAM接口的，这样主要方便sdram的刷新-fpga is based on the FIFO Table Tennis operation, and is behind SDRAM interface, This major update to the convenience sdram
Date : 2025-12-22 Size : 207kb User : eva
[VHDL-FPGA-Verilog] ram DL : 0: 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
Date : 2025-12-22 Size : 2kb User : nick
[VHDL-FPGA-Verilog] FPGA_two-way_IO DL : 0: FPGA Verilog,双向端口的研究,比较全,由ASSIGN和ALWAYS模块组成,测试可用-FPGA Verilog, bi-directional port studies comparing full-, and ALWAYS by ASSIGN modules, testing available
Date : 2025-12-22 Size : 113kb User : 鲍纯贝
[VHDL-FPGA-Verilog] Wave_ROM DL : 0: 基于RAm的FPGA实现DDS,有测试文件-Ram realize the FPGA-based DDS, have the test paper
Date : 2025-12-22 Size : 5kb User : xsj
[VHDL-FPGA-Verilog] T4_sdram_control DL : 0: verilog语言利用FPGA控制SDRAM，相信很多朋友都需要快下载吧-control FPGA Verilog language use SDRAM, believe that many of my friends need to download it faster
Date : 2025-12-22 Size : 19kb User : 杜菲
[VHDL-FPGA-Verilog] memio DL : 0: 最新VHDL 模块，实现对SRAM的控制，能直接用在ALTEAR XILLIX 等 FPGA上，-Latest VHDL modules to realize the control of SRAM can be directly used for ALTEAR XILLIX such as FPGA, the
Date : 2025-12-22 Size : 7kb User : 骑士
[VHDL-FPGA-Verilog] SDR_SDRAM_controler_verilog DL : 0: 可以用的通用SDRAM控制器,可以用在FPGA上,是SDR类型的-Can use the generic SDRAM controller can be used in the FPGA, the SDR is the type of
Date : 2025-12-22 Size : 9kb User : 郑宏超
[VHDL-FPGA-Verilog] sram_control DL : 0: verilog编写fpga与片外SRAM通信模块-Verilog FPGA with the preparation of SRAM chip communication module
Date : 2025-12-22 Size : 409kb User : 宇天
[VHDL-FPGA-Verilog] RAM DL : 0: 双口RAM与PXI总线接口设计，包括接口控制。-Dual-port RAM with PXI bus interface design, including interface control.
Date : 2025-12-22 Size : 1.16mb User : zwt
[VHDL-FPGA-Verilog] RAM DL : 0: 用VerilogHDL写的ram程序，对初学者会有帮助。-Writing the ram with VerilogHDL procedures will be helpful for beginners.
Date : 2025-12-22 Size : 265kb User : Blakeu
[VHDL-FPGA-Verilog] RS232capture DL : 0: This approach, we feel, came very close to obtaining an image from the camera OV7620. Before we tried to capture a camera signal, we successfully transferred a test image from the FPGA s onboard RAM modules through RS232 to the PC program. This file do it.
Date : 2025-12-22 Size : 39kb User : Joelmir J Lopes
[VHDL-FPGA-Verilog] ram DL : 0: ram的vhdl源代码在colloy实现-ram in the vhdl source code to achieve colloy
Date : 2025-12-22 Size : 1.83mb User : mamou
[VHDL-FPGA-Verilog] DDR_SDRAM DL : 0: DDR RAM控制器的VHDL源码, 实现平台是Lattice FPGA-DDR RAM controller VHDL source code, the realization of Lattice FPGA platform is
Date : 2025-12-22 Size : 661kb User : 黄达
[VHDL-FPGA-Verilog] ug_ram DL : 0: RAM design for FPGA in verilog
Date : 2025-12-22 Size : 283kb User : NguyenViet
[VHDL-FPGA-Verilog] ram DL : 0: 使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上用硬件描述语言实现一个RAM存储器。-The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware description language to achieve a RAM memory.
Date : 2025-12-22 Size : 194kb User : Daisy
[VHDL-FPGA-Verilog] actel-fpga-double-port-ram DL : 0: 基于Actel FPGA的双端口RAM设计--周立功单片机-Actel FPGA-based dual-port RAM design- ZLG MCU
Date : 2025-12-22 Size : 265kb User : fei
[VHDL-FPGA-Verilog] FPGA-RAM-Verilog DL : 0: 用Verilog语言编写的FPGA，对波形数据用RAM存储-Using Verilog language FPGA, using the waveform data stored in RAM
Date : 2025-12-22 Size : 4.62mb User : 何恒盛

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