Writing the ram with VerilogHDL procedures will be helpful for beginners.

RAM
...\db
...\..\prev_cmp_RAM.asm.qmsg
...\..\prev_cmp_RAM.eda.qmsg
...\..\prev_cmp_RAM.fit.qmsg
...\..\prev_cmp_RAM.map.qmsg
...\..\prev_cmp_RAM.qmsg
...\..\prev_cmp_RAM.sim.qmsg
...\..\prev_cmp_RAM.tan.qmsg
...\..\RAM.asm.qmsg
...\..\RAM.cbx.xml
...\..\RAM.cmp.bpm
...\..\RAM.cmp.cdb
...\..\RAM.cmp.ecobp
...\..\RAM.cmp.hdb
...\..\RAM.cmp.logdb
...\..\RAM.cmp.rdb
...\..\RAM.cmp.tdb
...\..\RAM.cmp0.ddb
...\..\RAM.cmp_bb.cdb
...\..\RAM.cmp_bb.hdb
...\..\RAM.cmp_bb.logdb
...\..\RAM.cmp_bb.rcf
...\..\RAM.dbp
...\..\RAM.db_info
...\..\RAM.eco.cdb
...\..\RAM.eda.qmsg
...\..\RAM.eds_overflow
...\..\RAM.fit.qmsg
...\..\RAM.hier_info
...\..\RAM.hif
...\..\RAM.map.bpm
...\..\RAM.map.cdb
...\..\RAM.map.ecobp
...\..\RAM.map.hdb
...\..\RAM.map.logdb
...\..\RAM.map.qmsg
...\..\RAM.map_bb.cdb
...\..\RAM.map_bb.hdb
...\..\RAM.map_bb.logdb
...\..\RAM.pre_map.cdb
...\..\RAM.pre_map.hdb
...\..\RAM.psp
...\..\RAM.pss
...\..\RAM.rtlv.hdb
...\..\RAM.rtlv_sg.cdb
...\..\RAM.rtlv_sg_swap.cdb
...\..\RAM.sgdiff.cdb
...\..\RAM.sgdiff.hdb
...\..\RAM.signalprobe.cdb
...\..\RAM.sim.hdb
...\..\RAM.sim.qmsg
...\..\RAM.sim.rdb
...\..\RAM.sim_ori.vwf
...\..\RAM.sld_design_entry.sci
...\..\RAM.sld_design_entry_dsc.sci
...\..\RAM.syn_hier_info
...\..\RAM.tan.qmsg
...\..\RAM.tis_db_list.ddb
...\..\wed.wsf
...\RAM.asm.rpt
...\RAM.done
...\RAM.eda.rpt
...\RAM.fit.rpt
...\RAM.fit.smsg
...\RAM.fit.summary
...\RAM.flow.rpt
...\RAM.map.rpt
...\RAM.map.summary
...\RAM.pin
...\RAM.pof
...\RAM.qpf
...\RAM.qsf
...\RAM.qws
...\RAM.sim.rpt
...\RAM.sof
...\RAM.tan.rpt
...\RAM.tan.summary
...\RAM.v
...\RAM.v.bak
...\RAM.vwf
...\simulation
...\..........\modelsim
...\..........\........\RAM.vo
...\..........\........\RAM_modelsim.xrf
...\..........\........\RAM_v.sdo

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