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[VHDL-FPGA-Verilog] dianji DL : 0: 基于FPGA系统的步进电机控制，内涵详细的源代码-FPGA-based system of stepper motor control, detailed content of the source code! !
Date : 2025-12-25 Size : 62kb User : 刘嵘
[VHDL-FPGA-Verilog] K163_addition DL : 0: elliptic curve in GF2m
Date : 2025-12-25 Size : 1kb User : endah
[VHDL-FPGA-Verilog] K163_point_multiplication DL : 0: elliptic curve in GF2m
Date : 2025-12-25 Size : 2kb User : endah
[VHDL-FPGA-Verilog] ddfs DL : 0: vhdl编的dds函数发生器，完成sin(x)曲线的生成-vhdl function generator dds compiled to complete the sin (x) curve is generated
Date : 2025-12-25 Size : 89kb User : 王晓虎
[VHDL-FPGA-Verilog] ecp233_1 DL : 0: elliptic curve processor b-233, include test bench & test vector.
Date : 2025-12-25 Size : 89kb User : tiger
[VHDL-FPGA-Verilog] ntc DL : 0: NTC电阻在VERILOG HDL中的曲线表，使用1MA恒流源供电，用AD对其采集电压，并以12BIT形式输出查表即可达到实际温度值，本表占用450个12位存储单元-NTC resistor VERILOG HDL in the curve of the table, use the 1MA current source power supply voltages were collected with AD and in the form of the output look-up table 12BIT can be achieved by the actual temperature values, the table occupies 450 12-bit memory cell
Date : 2025-12-25 Size : 88kb User : chenwl
[VHDL-FPGA-Verilog] Handbook_elliptic_curve_cryptography DL : 0: A wnice to guide to stat Elliptic Curve Cryptography
Date : 2025-12-25 Size : 4.98mb User : kalidas
[VHDL-FPGA-Verilog] ELIPTIC DL : 0: Matlab Security Eliptic curve crypto Matlab Security Eliptic curve crypto Matlab Security Eliptic curve crypto Matlab Security Eliptic curve crypto Matlab Security Eliptic curve crypto Matlab Security Eliptic curve crypto Matlab Security Eliptic curve crypto Matlab Security Eliptic curve crypto -Matlab Security Eliptic curve cryptoMatlab Security Eliptic curve cryptoMatlab Security Eliptic curve cryptoMatlab Security Eliptic curve cryptoMatlab Security Eliptic curve cryptoMatlab Security Eliptic curve cryptoMatlab Security Eliptic curve cryptoMatlab Security Eliptic curve cryptoMatlab Security Eliptic curve cryptoMatlab Security Eliptic curve cryptoMatlab Security Eliptic curve cryptoMatlab Security Eliptic curve cryptoMatlab Security Eliptic curve cryptoMatlab Security Eliptic curve cryptoMatlab Security Eliptic curve cryptoMatlab Security Eliptic curve crypto
Date : 2025-12-25 Size : 6.25mb User : sakthivel
[VHDL-FPGA-Verilog] Point_Doubling_4.0.vhd DL : 0: point doubling for ECC tripling oriented curve -point doubling for ECC tripling oriented curve
Date : 2025-12-25 Size : 2kb User : Ahmed Alkaff
[VHDL-FPGA-Verilog] LCD-point DL : 0: 在液晶屏幕上任意打点，画圆，可用于曲线显示驱动程序-Any dot on the LCD screen, draw a circle, the curve can be used for display driver
Date : 2025-12-25 Size : 23kb User : 刁杰
[VHDL-FPGA-Verilog] control DL : 1: 该程序描述了运用FPGA进行控制的S形曲线和其他传统加减速控制曲线方法的控制曲线比较研究。-This program is compiled in matlab circumstance。Describing the approach of S-curve control method in FPGA in machine controlling.
Date : 2025-12-25 Size : 780kb User : 赵九洲
[VHDL-FPGA-Verilog] -Elliptic DL : 0: We present elliptic curve cryptography (ECC) coprocessor, which is dual-field processor with projective coordinator. We have implemented architecture for scalar multiplication, which is key operation in elliptic curve cryptography. Our coprocessor can be adapted both prime field and binary field, also contains a control unit with 256 bit serial and parallel operations , which provide integrated highthroughput with low power consumptions. Our scalar multiplier architecture operation is perform base on clock rate and produce better performance in term of time and area compared to similar works. We used Verilog for programming and synthesized using Xilinx Vertex II Pro devices. Simulation was done with Modelsim XE 6.1e, VLSI simulation software from Mentor Graphics Corporation especially for Xilinx devices.
Date : 2025-12-25 Size : 114kb User : 陳曉慧
[VHDL-FPGA-Verilog] Motion_control DL : 2: 用verilog语言编写的步进电机加减速控制算法，可选择梯形曲线或S型曲线算法-Verilog language stepper motor acceleration and deceleration control algorithm, you can choose the trapezoidal curve or S-curve algorithm
Date : 2025-12-25 Size : 1.64mb User : taocheng
[VHDL-FPGA-Verilog] A7105-Datasheet-v1.1 DL : 0: 无线A7105说明书 0.0 Initial issue. 0.1 Modified specification and add section for TX power setting 0.2 Add top marking info., reflow profile, Carry tape & reel dimensi 0.3 Modify description of state machine and FIFO mode Rename IRQS1/IRQS2 to GIO1S/GIO2S Rename GPIO1/GPIO2 to GIO1/GIO2 Add Easy FIFO mode, Segment FIFO mode Delete thermal sensor function / external voltage measuremen Delete TWWS function Add State diagram of quick/normal/power saving FIFO mode Add State diagram of Direct mode Rename Master Clock FCSCK to FMCLK Modify data rate support from 1K~500K to 2K ~ 500K 1.0 Revise description of state machine and FIFO mode Remove un-necessary components of application circuit Add RSSI curve Add layout guidance 1.1 Revise min. operation voltage from 1.9V to 2.0V Revise typical TX current (0dBm) from 19mA to 20mA-0.0 Initial issue. 0.1 Modified specification and add section for TX power setting 0.2 Add top marking info., reflow profile, Carry tape & reel dimensi 0.3 Modify description of state machine and FIFO mode Rename IRQS1/IRQS2 to GIO1S/GIO2S Rename GPIO1/GPIO2 to GIO1/GIO2 Add Easy FIFO mode, Segment FIFO mode Delete thermal sensor function/external voltage measuremen Delete TWWS function Add State diagram of quick/normal/power saving FIFO mode Add State diagram of Direct mode Rename Master Clock FCSCK to FMCLK Modify data rate support from 1K~500K to 2K ~ 500K 1.0 Revise description of state machine and FIFO mode Remove un-necessary components of application circuit Add RSSI curve Add layout guidance 1.1 Revise min. operation voltage from 1.9V to 2.0V Revise typical TX current (0dBm) from 19mA to 20mA
Date : 2025-12-25 Size : 1.88mb User : 苏春明
[VHDL-FPGA-Verilog] Elliptic_Curve_Group_latest.tar DL : 0: 椭圆曲线群的核心是计算在椭圆曲线群的两个元素的加入，并在椭圆曲线组相同的元素的加入。-The Elliptic Curve Group core is for computing the addition of two elements in the elliptic curve group, and the addition of identical elements in the elliptic curve group.
Date : 2025-12-25 Size : 567kb User : ke
[VHDL-FPGA-Verilog] Tate_Bilinear_Pairing_latest.tar DL : 0: The Tate Bilinear Pairing core is for calculating Tate bilinear pairing especially on super-singular elliptic curve in affine coordinates defined over a Galois field , whose irreducible polynomial is . (For improving security, an irreducible polynomial with higher degree might be used in the future.) -The Tate Bilinear Pairing core is for calculating Tate bilinear pairing especially on super-singular elliptic curve in affine coordinates defined over a Galois field , whose irreducible polynomial is . (For improving security, an irreducible polynomial with higher degree might be used in the future.)
Date : 2025-12-25 Size : 482kb User : ke
[VHDL-FPGA-Verilog] SIN DL : 0: 使用rom生成sin曲线，VHDL实验课上做的实验，适合初学者。-Sin curve generated using the rom, VHDL experimental class to do the experiment, suitable for beginners.
Date : 2025-12-25 Size : 431kb User : haby
[VHDL-FPGA-Verilog] code DL : 0: 若输入信道的各符号等概出现，求该信道的互信息量 • 画出不同信噪比下的互信息量变化的曲线，以M为参数，画一簇曲线（其中加上一条 AWGN信道容量曲线作对比） • 调整函数a=f(x)，使当x=si时，a=iA‐b，b也为一实常数，在A和 不变的情况下，互信息量随b的变化情况是什么趋势？ • b的取值对互信息量随信噪比的变化曲线的影响-If the input channel of the symbols, such as concept, for the channel mutual information- painting a different signal to noise ratio of the mutual information quantity curve, in M for parameters and draw a cluster of curves (which plus a AWGN channel capacity curves for comparison)- adjustment function a=f (x), so that when x =si. B a=iA-, B also is a real constant, unchanged in a and sigma, mutual information quantity changes with B is what trend? The influence of the value of B on the mutual information and the change curve of the signal to noise ratio
Date : 2025-12-25 Size : 1kb User : 王先生
[VHDL-FPGA-Verilog] fen_v67 DL : 0: MIT Artificial Intelligence Laboratory identification of the target source, There CDF trigonometric curve / 3D graphs, Can realize the two-dimensional data clustering.
Date : 2025-12-25 Size : 7kb User : sansiehuigeng
[VHDL-FPGA-Verilog] ms411 DL : 0: D-S evidence theory data fusion, Including principal component analysis, factor analysis, Bayesian analysis, There is a well attenuation curve as input to calculate its seismic waves.
Date : 2025-12-25 Size : 5kb User : liujengfenggang

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