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[VHDL-FPGA-Verilog] DDS小数分频 DL : 0: 文件列表(点击判断是否您需要的文件，如果是垃圾请在下面评价投诉): DDS小数分频 ...........\Block1.vhd.bak ...........\db ...........\..\add_sub_9mh.tdf ...........\..\DDS.asm.qmsg ...........\..\DDS.asm_labs.ddb ...........\..\DDS.cbx.xml ...........\..\DDS.cmp.bpm ...........\..\DDS.cmp.cdb ...........\..\DDS.cmp.ecobp ...........\..\DDS.cmp.hdb ...........\..\DDS.cmp.logdb ...........\..\DDS.cmp.rdb ...........\..\DDS.cmp.tdb ...........\..\DDS.cmp0.ddb ...........\..\DDS.cmp2.ddb ...........\..\DDS.cmp_bb.cdb ...........\..\DDS.cmp_bb.hdb ...........\..\DDS.cmp_bb.logdb ...........\..\DDS.cmp_bb.rcf ...........\..\DDS.dbp ...........\..\DDS.db_info ...........\..\DDS.eco.cdb ...........\..\DDS.eds_overflow ...........\..\DDS.fit.qmsg ...........\..\DDS.fnsim.cdb ...........\..\DDS.fnsim.hdb ...........\..\DDS.fnsim.qmsg ...........\..\DDS.hier_info ...........\..\DDS.hif ...........\..\DDS.map.bpm ...........\..\DDS.map.cdb ...........\..\DDS.map.ecobp ...........\..\DDS.map.hdb ...........\..\DDS.map.logdb ...........\..\DDS.map.qmsg ...........\..\DDS.map_bb.cdb ...........\..\DDS.map_bb.hdb ...........\..\DDS.map_bb.logdb ...........\..\DDS.pre_map.cdb ...........\..\DDS.pre_map.hdb ...........\..\DDS.psp ...........\..\DDS.pss ...........\..\DDS.rtlv.hdb ...........\..\DDS.rtlv_sg.cdb ...........\..\DDS.rtlv_sg_swap.cdb ...........\..\DDS.sgdiff.cdb ...........\..\DDS.sgdiff.hdb ...........\..\DDS.signalprobe.cdb ...........\..\DDS.sim.cvwf ...........\..\DDS.sim.hdb ...........\..\DDS.sim.qmsg ...........\..\DDS.sim.rdb ...........\..\DDS.sld_design_entry.sci ...........\..\DDS.sld_design_entry_dsc.sci ...........\..\DDS.syn_hier_info ...........\..\DDS.tan.qmsg ...........\..\prev_cmp_DDS.asm.qmsg ...........\..\prev_cmp_DDS.fit.qmsg ...........\..\prev_cmp_DDS.map.qmsg ...........\..\prev_cmp_DDS.sim.qmsg ...........\..\prev_cmp_DDS.tan.qmsg ...........\..\wed.wsf ...........\DDS.asm.rpt ...........\DDS.bdf ...........\DDS.done ...........\DDS.dpf ...........\DDS.fit.rpt ...........\DDS.fit.smsg ...........\DDS.fit.summary ...........\DDS.flow.rpt ...........\DDS.map.rpt ...........\DDS.map.summary ...........\DDS.pin ...........\DDS.pof ...........\DDS.qpf ...........\DDS.qsf ...........\DDS.sim.rpt ...........\DDS.sof ...........\DDS.tan.rpt ...........\DDS.tan.summary ...........\DDS.vhd ...........\DDS.vhd.bak ...........\DDS.vwf ...........\lpm_add_sub0.bsf ...........\lpm_add_sub0.inc ...........\lpm_add_sub0.tdf ...........\lpm_add_sub0_waveforms.html ...........\lpm_add_sub1.bsf ...........\lpm_add_sub1.inc ...........\lpm_add_sub1.tdf ...........\lpm_add_sub1_waveforms.html ...........\lpm_add_sub2.bsf ...........\lpm_add_sub2.inc ...........\lpm_add_sub2.tdf ...........\lpm_add_sub2_waveforms.html ...........\parallel_add0.bsf
Date : 2009-05-03 Size : 495.98kb User : beijbinghe@163.com
[VHDL-FPGA-Verilog] State.Machine DL : 0: State.Machine.Coding.Styles.for.Synthesis（状态机，英文,VHDL）-State.Machine.Coding.Styles.for.Synthesis (FSM, English, VHDL)
Date : 2025-12-16 Size : 121kb User :
[VHDL-FPGA-Verilog] time_display&alarm_clock DL : 0: 此为在实验板上通过的时钟闹铃程序，源码分别用ASM和VHDL描叙，但两程序功能不同。-this experiment for the board through the alarm clock procedures were used ASM source VHDL and depicts, but the two procedures different functions.
Date : 2025-12-16 Size : 2kb User : 陈谷
[VHDL-FPGA-Verilog] GWDVPB DL : 0: 基于VHDL语言的高精度频率计的设计,已通过实验测试-based on VHDL frequency precision of the design, experimental test
Date : 2025-12-16 Size : 2kb User : 钟声
[VHDL-FPGA-Verilog] MSP430UART DL : 0: 这是MSP430串口编程方面的资料，希望对大家有用。-This is the MSP430 serial programming the information, we hope that the right useful.
Date : 2025-12-16 Size : 26kb User : kite_comx
[VHDL-FPGA-Verilog] LC3-VHDL-another DL : 0: 另一套LC3 CPU VHDL源码及设计文档，对LC3进行了一些取舍和改造，比如NZP改为NZC，更贴近现实CPU硬件架构。按照ASM进行VHDL编码，更适合数字设计初学者学习。-Another set of LC3 CPU VHDL source code and design documents, of LC3 to a number of trade-offs and transformation, such as NZP changed NZC, more close to reality CPU hardware architecture. In accordance with the ASM to VHDL coding, digital design more suitable for beginners to learn.
Date : 2025-12-16 Size : 790kb User : guo
[VHDL-FPGA-Verilog] 32_16div DL : 0: 这是一个简单的除法器（32bit/16bit),采用移位相减法-This is a simple divider (32bit/16bit), using phase shift subtraction
Date : 2025-12-16 Size : 1kb User : 郭勇谅
[VHDL-FPGA-Verilog] SYNTHPIC.ZIP DL : 0: The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontroller. It is not, and is not intended as, a high fidelity circuit simulation. This package includes the following files. Note that the license agreement is stated in the main VHDL file, PICCPU.VHD and common questions are answered in the file SYNTHPIC.TXT Files: README.TXT This file.. SYNTHPIC.TXT Questions and Answers PICCPU.VHD Main processor VHDL file PICALU.VHD ALU for the PICCPU PICREGS.VHD Data memory PICROM.VHD Program memory (created by HEX2VHDL utility) PICTEST.VHD Simple test bench I used to do testing (optional) PICTEST.CMD My Viewlogic ViewSim command file (again, optional) TEST1.ASM First program I assembled and ran on it. TEST2.ASM Another test program.. TEST3.ASM Yet another.. TEST4.ASM Yet another.. TEST5.ASM Yet another.. TEST6.ASM Yet another.. HEX2VHDL.CPP Utility for converting -The Synthetic PICVerion 1.1This a VHDL synthesizable model of a simple PIC 16C5x microcontroller.It is not, and is not intended as, a high fidelity circuit simulation.This package includes the following files. Note that the license agreementis stated in the main VHDL file , PICCPU.VHD and common questions are answeredin the file SYNTHPIC.TXTFiles: README.TXT This file .. SYNTHPIC.TXT Questions and AnswersPICCPU.VHD Main processor VHDL filePICALU.VHD ALU for the PICCPUPICREGS.VHD Data memoryPICROM.VHD Program memory (created by HEX2VHDL utility) PICTEST.VHD Simple test bench I used to do testing (optional) PICTEST.CMD My Viewlogic ViewSim command file (again, optional) TEST1.ASM First program I assembled and ran on it.TEST2.ASM Another test program. . TEST3.ASM Yet another .. TEST4.ASM Yet another .. TEST5.ASM Yet another .. TEST6.ASM Yet another .. HEX2VHDL.CPP Utility for converting
Date : 2025-12-16 Size : 47kb User : likui
[VHDL-FPGA-Verilog] minimigJ_source_04_08_2008 DL : 0: Verilog, c and asm source codes of the Minimig system, a fpga implementation of the Amiga computer. Version minimig-j used on the Minimig fpga board.
Date : 2025-12-16 Size : 191kb User : lihard
[VHDL-FPGA-Verilog] memory_game.asm DL : 0: example for memory game in vhdl
Date : 2025-12-16 Size : 2kb User : ido
[VHDL-FPGA-Verilog] delay DL : 0: Asm routine for temporisation PIC
Date : 2025-12-16 Size : 1kb User : raouia
[VHDL-FPGA-Verilog] horloge DL : 0: Asm Routine for Horloge for PIC
Date : 2025-12-16 Size : 2kb User : raouia
[VHDL-FPGA-Verilog] lcd DL : 0: Asm routine for LCD drive with PIC 16F
Date : 2025-12-16 Size : 2kb User : raouia
[VHDL-FPGA-Verilog] movedata DL : 0: 按照一定格式把一段数据放在内存上，然后输出在屏幕上-my asm
Date : 2025-12-16 Size : 1kb User : lrgeid
[VHDL-FPGA-Verilog] spi.asm DL : 0: vhdl spi port configuration
Date : 2025-12-16 Size : 2kb User : mohamad
[VHDL-FPGA-Verilog] PILILED DL : 0: For pili light implement , with verilog design method.-In ASIC flow, use verilog to insted of 8051 ASM code design.
Date : 2025-12-16 Size : 6kb User : ananliu1
[VHDL-FPGA-Verilog] SystemVerilog DL : 0: 关于SYSTEMVERILOG的语法，一些例子-About SYSTEMVERILOG syntax, examples and so on. . . . . . .
Date : 2025-12-16 Size : 48.08mb User : 胡刚
[VHDL-FPGA-Verilog] 18-divide-8-divider DL : 0: 从ASM状态图可以看出，在state=0时，初始化参数，如果开始信号有效则载入被除数与除数，接着进入state=1状态，首先判断被除数寄存器的高九位是否大于除数，如果是则产生溢出信号，并回到此状态；否则被除数寄存器向左移一位，并进入state=2状态，同样先判断被除数寄存器的高九位是否大于除数,如果是则被数高九位减去除，并被除数最后一位置为1，并回到此状态；否则被除数寄存器向左移一位，并进入state=3状态, 同样先判断被除数寄存器的高六位是否大于除数,如果是则被数高九位减去除，并被除数最后一位置为1，并回到此状态；否则被除数寄存器向左移一位，并进入state=4状态,此时判断被除数寄存器的高9位是否大于除数,如果是则被数高九位减去除，并被除数最后一位置为1，并回到此状态；否则输出商res与余数yushu.,并回到state=0状态，等待下一个开始信号。-From state chart can be seen by ASM, state = 0, the initialization parameters, if the starting signal effectively is loaded with the divisor, then enter dividend state = 1 state, the first judge whether high dividend register more than nine by 0.14585278, if have spilling signal, and return to the state Otherwise dividend registers, and enter the move to the left, a state = 2 state, also be judged on whether the high dividend register more than nine by 0.14585278, if is number nine, and subtract except high dividend last position is 1, and return to the state Otherwise dividend registers, and enter the move to the left, a state = 3 state, also be judged on whether the high dividend register more than six by 0.14585278, if is number nine, and subtract except high dividend last position is 1, and return to the state Otherwise dividend registers, and enter the move to the left, a state = 4 state, at this time the judge dividend registers high 9 are outweighed by 0.14585278, if is numbe
Date : 2025-12-16 Size : 12kb User : Rain
[VHDL-FPGA-Verilog] diandongche.ASM DL : 0: 电动车控制器系统源代码程序或许有一点帮助-electric bicycle controller
Date : 2025-12-16 Size : 3kb User : 李华
[VHDL-FPGA-Verilog] LCD-Driver-And-Keyboard-char-Asm(www.bargh20.com) DL : 0: LCD Driver And Keyboard char Asm(www.bargh20.com)
Date : 2025-12-16 Size : 20kb User : vahid

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