Search - accumulator

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[VHDL-FPGA-Verilog] adder DL : 0: 加法器（使用verilog编写的）,虽然简单，但是这也是学习verilog最基础的东西！希望大家一起学习！-The accumulator (uses the verilog compilation), although it is simple, but this also is studies most foundation of the verilog! Hopes everybody studies together!
Date : 2025-12-14 Size : 131kb User :
[VHDL-FPGA-Verilog] dianzizhong DL : 0: 这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以直接下载,已经编译通过!-This is my learning process in the middle of the 10-minute program, containing various clock module and the counter, accumulator, and can download, compile!
Date : 2025-12-14 Size : 538kb User : 刘恒辉
[VHDL-FPGA-Verilog] 100vhdl DL : 0: 100个VHDL程序,关于基本的模块,有累加器等-100 VHDL procedures, on the basic module, accumulator, etc. have
Date : 2025-12-14 Size : 231kb User :
[VHDL-FPGA-Verilog] accumulator DL : 0: 实现累加器的verilog源码，广泛应用在通信电路设计中-The realization of accumulator Verilog source, widely used in communication circuit design
Date : 2025-12-14 Size : 1kb User : 文明
[VHDL-FPGA-Verilog] sum_ten DL : 0: 十位累加器,EDA,FPGA,DDS信号发生器的相位累加器,可用.-Accumulator 10, EDA, FPGA, DDS signal generator of the phase accumulator can be used.
Date : 2025-12-14 Size : 3kb User : seasonroad
[VHDL-FPGA-Verilog] division DL : 0: 分别用分频比交错法及累加器分频法完成非整数分频器设计。-Points were staggered method and frequency than the frequency accumulator law to complete the design of non-integer divider.
Date : 2025-12-14 Size : 28kb User : 旭东
[VHDL-FPGA-Verilog] X4 DL : 0: 4位乘法累加器，有需要的下吧，其他位的可以自行修改~-Multiplication accumulator 4
Date : 2025-12-14 Size : 1kb User : 李才
[VHDL-FPGA-Verilog] DDS DL : 0: 自己在Quartus下用VHDL编写的一个DDS程序。包括寄存器，累加器，波形存储器-In Quartus using VHDL procedures for the preparation of a DDS. Including the register, accumulator, waveform memory
Date : 2025-12-14 Size : 343kb User : ice
[VHDL-FPGA-Verilog] 65jie DL : 0: 串并FIR滤波器设计:并行FIR滤波器具有速度快、容易设计的特点，但是要占用大量的资源。在多阶数的亚高频系统设计中，使用并行结构并不合算，但亚高频系统需要较高的处理速度，而串行架构往往达不到要求，因此，结合串并这两种设计方法的长处，在使用较少的硬件资源的同时实现了较高的处理速度，这里说明一种65阶八路并行、支路串行FIR滤波器的设计（实际使用了1个乘法器，8个乘累加器，一个累加器）。-String and FIR filter design: parallel FIR filter with a fast, easy design features, but I want to use up a lot of resources. In a multi-order high-frequency sub-system design, the use of parallel structures and uneconomical, but the high frequency sub-system requires a higher processing speed, and the serial structure often fail, therefore, combines both the design of string and method' s strengths, using less hardware resources to achieve a high processing speed of 65 bands here that a parallel eight-way, slip serial FIR filter design (the actual use of a multiplier, 8 by accumulator, an accumulator).
Date : 2025-12-14 Size : 12kb User : 南才北往
[VHDL-FPGA-Verilog] dds_easy DL : 0: 直接频率合成DDS模块的ise工程，可以直接下载，在Spartan3/Spartan3E上验证通过。该DDS模块可以产生双通道的不同频率的正弦波，也可以产生同频的任意相位差的相移波形。本模块累加器位数为32位，可以产生12位相位精度12位量化精度的正弦波。该设计例化一个Block Ram，为节省储存空间仅需要储存1/4周期的数据。根据需要，可以重新修改数据，改变波形。-DDS direct frequency synthesizer module ，ise project, can be directly downloaded through the Spartan3/Spartan3E and tested successfully. The DDS module can generate two-channel sine wave of different frequency, or produce the same frequency arbitrary waveform phase difference of the phase shift. There is a 32-bit accumulator to generate 12 bit phase-precision 12-bit quantization precision of the sine wave. Cases the design of a Block Ram, in order to save storage space need to store only 1/4 cycle of data. Necessary, can modify data, change the waveform.
Date : 2025-12-14 Size : 460kb User : 郭先生
[VHDL-FPGA-Verilog] daima DL : 0: 用VHDL语言设计一个8位加法器：在八位加法器代码一中：加法器是由两个4位二进制加法器U1和U2组成的8位加法器逻辑电路，其中U1用来装载8位加法器中两个加数的低4位，而U2则用来装载高4位。在设计4位加法器时，定义输入信号量CIN、A、B以及输出信号量S、Cout。定义信号量SINT/AA/BB，将加数A和0并置后赋给AA，加数B和0并置后赋给BB，形成5位二进制数，这是为在做加法时发生溢出所做的处理，然后将加数AA与BB以及进位Cin相加赋给SINT，并将SINT的低4位赋给加数和S输出，同时将SINT最高位传送给Cout输出。在设计8位加法器时，定义一个信号量CARRY，将4位加法器U1的COUT赋给CARRY，再将CARRY的值赋给4位加法器U2的进位位Cin，8位加法器的高4位和低4位分别来自于4位加法器U2和U1。而在八位加法器代码二中：8位加法器的设计不使用底层文件，直接设计为8位与8位的相加，该种方法在设计上更为简洁。在实验硬件连接上，可以使用LED七段数码管显示所得结果，使结果显示更为清晰明了。 -With VHDL language design 8 accumulators: in eight accumulator codes in one: The accumulator is 8 accumulator logic circuit which is composed of two 4 binary system accumulator U1 and U2, U1 uses for to load in 8 accumulators two addend low 4, but U2 uses for to load high 4. When designs 4 accumulators, the definition input signal measures CIN, A, B as well as the output signal measures S, Cout. The definition signal measures SINT/AA/BB, after addend A and 0 juxtapositions, bestows on for AA, after addend B and 0 juxtapositions, bestows on for BB, forms 5 binary system number, this is for when does the addition has processing which the overflow does, then as well as carries Cin addend AA and BB to levy additional taxes for SINT, and the SINT low 4 taxes for the addend and the S output, simultaneously transmits the SINT highest order to the Cout output. When designs 8 accumulators, defines a signal to measure CARRY, bestows on 4 accumulator U1 COUT for CARRY, bestows on again the CARRY
Date : 2025-12-14 Size : 9kb User : SAM
[VHDL-FPGA-Verilog] DDS DL : 0: 基于EPM7128的数字合成信号发生器（DDS）设计。通过对EPM7128编程，组合出地址累加器、数据锁存器、256*8位ROM空间。外接DA可实现正弦波输出功能-EPM7128-based signal generator for digital synthesis (DDS) design. EPM7128 through programming, the combination of address accumulator, data latches, 256* 8 ROM space. DA external sine wave output function can be realized
Date : 2025-12-14 Size : 346kb User : xiaoyu
[VHDL-FPGA-Verilog] laba2_acc DL : 0: Accumulator realization on VHDL
Date : 2025-12-14 Size : 191kb User : Sima
[VHDL-FPGA-Verilog] leijia DL : 0: 二进制累加器：实现多个二进制数累加，有复位，按键防反弹等功能（每按一次作一次累加，累加数由若干位开关表示，结果由若干位LED输出。-Binary accumulator: accumulation of multiple binary number, there are reset, key features such as anti-bounce (each time I press to make a cumulative, accumulate a number by a number of digital switches that result by a number of digital LED output.
Date : 2025-12-14 Size : 381kb User : dujcel
[VHDL-FPGA-Verilog] DDS_VHDL DL : 0: 基于FPGA环境的直接数字频率合成器的源代码-16 accumulator
Date : 2025-12-14 Size : 252kb User : 姚强
[VHDL-FPGA-Verilog] multiplier-accumulator(vhdl) DL : 0: 用VHDL语言描述和实现乘法累加器设计,4位的被乘数X和4位的乘数Y输入后，暂存在寄存器4位的寄存器A和B中，寄存器A和B的输出首先相乘，得到8位乘积，该乘积再与8位寄存器C的输出相加，相加结果保存在寄存器C中。寄存器C的输出也是系统输出Z。(原创，里面有乘法部分和累加部分可以单独提出来，很好用) -With the VHDL language to describe the design and realization of multiplier-accumulator, four of multiplicand X and 4-bit multiplier Y input, the temporary 4-bit registers in the register A and B, registers A and B multiplied by the output of the first, to be 8-bit product, the product further with the 8-bit output of register C, the sum of, the sum of the results stored in register C,. The output register C is also the system output Z. (Original, which are multiply and accumulate some part may be raised separately, very good use)
Date : 2025-12-14 Size : 945kb User : jlz
[VHDL-FPGA-Verilog] project_Giovanni_DAliesio DL : 0: code for accumulator multiplier
Date : 2025-12-14 Size : 1.97mb User : maysaa
[VHDL-FPGA-Verilog] Accumulator DL : 0: 数字逻辑设计中累加器的开发源代码，开发环境为Quartus-Accumulator in Quartus
Date : 2025-12-14 Size : 311kb User : 陈轶博
[VHDL-FPGA-Verilog] Verilog-Accumulator DL : 0: the folder contains two files written by Verilog HDL. the first one is an implementation of an accumulator that takes serial data as an input, and its output will be an accumulated sum of each consecutive four input samples. the second file is a test bench for the first file to test its operation
Date : 2025-12-14 Size : 1kb User : sawsan
[VHDL-FPGA-Verilog] Accumulator DL : 0: An 8-bit Accumulator with an adder module in Verilog HDL. You can change the bus width decoding the adder.
Date : 2025-12-14 Size : 6.66mb User : Patrick Go

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